fpga-tidbits

<?xml version="1.0" encoding="UTF-8"?>
<root versionMajor="1" versionMinor="6">
  <kernel name="GenericSDAccelWrapperTop" language="ip" vlnv="xilinx.com:RTLKernel:GenericSDAccelWrapperTop:1.0" attributes="" preferredWorkGroupSizeMultiple="0" workGroupSize="1" debug="true" compileOptions=" -g" profileType="none" interrupt="true">
    <ports>
      <port name="s_axi_control" mode="slave" range="0x1000" dataWidth="32" portType="addressable" base="0x0"/>
      <port name="m_axi_gmem" mode="master" range="0xFFFFFFFF" dataWidth="64" portType="addressable" base="0x0"/>
    </ports>
    <args>
      <arg name="src" addressQualifier="1" id="0" port="m_axi_gmem" size="0x8" offset="0x18" hostOffset="0x0" hostSize="0x8" type="int*"/>
      <arg name="dst" addressQualifier="1" id="1" port="m_axi_gmem" size="0x8" offset="0x24" hostOffset="0x0" hostSize="0x8" type="int*"/>
      <arg name="nwords" addressQualifier="0" id="2" port="s_axi_control" size="0x4" offset="0x30" hostOffset="0x0" hostSize="0x4" type="int"/>
    </args>
  </kernel>
</root>