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fpga-tidbits

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Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.

[gitignore] update

Erling Jellum · Dec 17, 2020, 5:36 PM UTC

59b2d0bce095

[cpp] ops. Add some drivers I accidentally deleted earlier

Erling Jellum · Dec 17, 2020, 5:31 PM UTC

6f7a8db97d30

[TestMultiChanSum] Added automatic integration tests for TestMultiChanSum

erling · Dec 13, 2020, 5:23 PM UTC

7bc9744e3b50

[TestMultiChanSum] Now works. Had to make really performance degrading quick-fix in TesterWrapper. Now spends 2 CC per word read from mem. Should be fixed, but only affects simulatio

erling · Dec 13, 2020, 5:06 PM UTC

b92aff4c5d4a

[CI] add script to run all tests

erling · Dec 10, 2020, 10:09 AM UTC

e30079911664

[CI] Add integration tests for Sum, RegOps, BRAM and BRAMMasker

erling · Dec 10, 2020, 9:49 AM UTC

95d79aa9a3c6

[CI] add some integration test stuff

erling · Dec 9, 2020, 5:55 PM UTC

b218fc2fb4dd

[TestBRAM] TestBRAM and TestBRAMMasked passes simple Verilator tests

erling · Dec 9, 2020, 5:34 PM UTC

3f3a873b5f00

[TestGather] Still not properly working. Leave it for now

erling · Dec 9, 2020, 11:13 AM UTC

3582994caadf

[TestGather] Fix typo and add test for it

erling · Dec 8, 2020, 3:35 PM UTC

dc78b26b7124

[DualPortBRAM] make an external interface with correct naming and update all occurences

erling · Dec 8, 2020, 12:18 PM UTC

2d78f163ef30

[chisel3] add cloneType on some bundles

erling · Dec 8, 2020, 9:42 AM UTC

2f740365460c

[chisel3] change from != to =/=

erling · Dec 7, 2020, 11:50 AM UTC

194bd3784774

[TestGather] fix issues and initialize references. Compiles to Verilog/FIRRTL

erling · Dec 7, 2020, 11:48 AM UTC

38c0f7d665ce

merge

erling · Dec 7, 2020, 9:56 AM UTC

e4a3b2cab964

[TestRegOps] initial port

erling · Dec 7, 2020, 9:54 AM UTC

ef85a5707257

[TestGather] fix issues with reference not fully initialize. Some queues dont have their ready/valid io initialized. Check chisel2 source code to find my bug

Erling Jellum · Dec 6, 2020, 12:53 PM UTC

b592e3b7d39e

[verilator] clock->clk again2

Erling Jellum · Dec 6, 2020, 12:30 PM UTC

83d678834532

[TestRegOps] now works with Verilator

Erling Jellum · Dec 6, 2020, 12:29 PM UTC

6c30c7615ce3

[TestGather] Seems to compile. But fails at generating the RegDriver. Should be a quick fix

erling · Dec 4, 2020, 5:00 PM UTC

c4fef77b057a

[TestGather] Start fixing this test. Chisel HW vs Chisel Type errors

erling · Dec 4, 2020, 2:48 PM UTC

930547831efa

[Tests] add remaining source files needed for rest of the Tests. Syntax fixed

erling · Dec 4, 2020, 11:17 AM UTC

4403c9baeef9

[utils] Add a utils package for useful operations and a testbench

erling · Dec 4, 2020, 11:16 AM UTC

0ec316313ca7

Undo changing of the IP-COre for ZedBoard and do few syntactical updates on DMA SG

erling · Dec 3, 2020, 4:00 PM UTC

e26471f02baf

[Tests] Add OCM and DMA SG stuff needed by the rest of the tests

erling · Dec 3, 2020, 3:51 PM UTC

94b97f2eda51

[Tests] fix syntactical issues with the rest of the tests

erling · Dec 3, 2020, 3:50 PM UTC

01042c2201fb

[Tests] Add rest of the tests

erling · Dec 3, 2020, 3:35 PM UTC

5331e919b13d

[AXI RegFile] Fixed typo breaking the design. Added a small Testbench for testing the AXI interface to the CSR. Add option to not generate reg driver (like if we are instantiating something in a TEstBench)

erling · Dec 3, 2020, 3:30 PM UTC

7eeca8d94fbe

[vivado ip-xact] undo mistaken commit changing the ZedboardWrapper

erling · Dec 2, 2020, 5:28 PM UTC

1b3b0671dfd1

[MVP] Messy commit. Trying to get TestSum to work on actual HW. Currently the problem is that csr_AWADDR is optimized away for some reason by Vivado. It is present in Verilog

erling · Dec 2, 2020, 5:24 PM UTC

b5da44835a31

[AXI-naming] Update AXILite

erling · Dec 2, 2020, 11:03 AM UTC

90cddcc3498c

[AXI-naming] make new AXIExternalIF with correct signal naming

erling · Dec 2, 2020, 10:38 AM UTC

1e8dca579365

[AXI-naming] fix instance naming on AXIPlatformWrapper

erling · Nov 30, 2020, 2:41 PM UTC

c8394b54daf1

[Verilog] fix chiselargs for verilog

erling · Nov 30, 2020, 2:41 PM UTC

51ebce415de5

TestSum verilator emulation works

erling · Nov 30, 2020, 1:50 PM UTC

c3f07044375e

[verilatedtesterdriver] clk -> clock

erling · Nov 30, 2020, 11:49 AM UTC

936038a57068

--no-edit

erling · Nov 30, 2020, 9:39 AM UTC

836c0de1ea7f

Update sbt so we get iotesters. Use iotesters to create c++ backend via verilator

erling · Nov 30, 2020, 9:39 AM UTC

017bfe9a85b2

Now compiles but I am unable to generate c- (verilator? backend)

erling · Nov 27, 2020, 7:06 PM UTC

64f5d07c7714

Fix GenericMemoryReq/Resp by making Wire factory in companion object

erling · Nov 27, 2020, 4:23 PM UTC

33c2af41f22e

Fix some I/O typos and fix some reg driver issues

erling · Nov 27, 2020, 9:30 AM UTC

45f5cef9dfb7

Remove Chisel mock queue from Q_SRL not allowed in BlackBox

erling · Nov 27, 2020, 8:19 AM UTC

f8e753d3148f

Fixed all syntactical stuff

erling · Nov 27, 2020, 8:18 AM UTC

05d3866897f4

Add some files that actually where needed again

erling · Nov 20, 2020, 7:58 AM UTC

e71dbca446aa

More chisel3 stuff

erling · Nov 20, 2020, 7:57 AM UTC

922c5024348e

merge in removing all except mvp for TestSum

erling · Nov 19, 2020, 9:27 AM UTC

8f0b9a835f60

Remove everything except most basic example to port to chisel3

Erling Jellum · Nov 18, 2020, 8:43 PM UTC

69e098d9daeb

ADd hardcoded path and use newer sbt version

erling · Nov 18, 2020, 4:45 PM UTC

817ac8e30038

Begin tedious work of porting to chisel3

erling · Nov 18, 2020, 4:25 PM UTC

0b94fd4e120e

[AXI] wire up data from write burst adapter

Yaman Umuroglu · Jun 23, 2019, 1:41 PM UTC

a6b4c6ce090e

[AXI] wire up write burst adapter in AXIPlatformWrapper

Yaman Umuroglu · Jun 23, 2019, 10:56 AM UTC

e49e532bdb08

[AXI] experimental new component to enable AXI write bursts

Yaman Umuroglu · Jun 23, 2019, 10:56 AM UTC

45f80d305b3b

[U96, ZCU104] use same driver for PYNQU96 and PYNQZCU104

Yaman Umuroglu · Jun 22, 2019, 10:13 AM UTC

8b69f9a2b74e

[ZCU104] add ZCU104 platforms to TidbitsMakeUtils

Yaman Umuroglu · Jun 22, 2019, 10:07 AM UTC

6fe696d10cb8

[ZCU104] add platform wrappers for PYNQ CC and non-CC variants on ZCU104

Yaman Umuroglu · Jun 22, 2019, 10:07 AM UTC

d760335e07a3

[CC] typo fix

Yaman Umuroglu · Jun 4, 2019, 8:20 AM UTC

2a85749d6b44

[PYNQU96CC] typo fix

Yaman Umuroglu · Jun 3, 2019, 10:46 PM UTC

c2a4daabfcca

expose coherency indicator through PlatformWrapperParams

Yaman Umuroglu · Jun 3, 2019, 10:29 PM UTC

8176c1fade3e

add is_coherent() and phys2virt() to wrapper, enable for xlnk

Yaman Umuroglu · Jun 3, 2019, 10:22 PM UTC

0ce319a9a8bc

[PYNQU96CC] add cache-coherent, single-port version of PYNQU96

Yaman Umuroglu · Jun 3, 2019, 10:21 PM UTC

e5a9d9cef893

Revert "set up PYNQU96 mem port 0 signals for coherency"

Yaman Umuroglu · Jun 3, 2019, 9:52 PM UTC

675468bd7a55

Revert "go back to single memport TestCopy to prep for $-coherency tests"

Yaman Umuroglu · Jun 3, 2019, 9:52 PM UTC

89586da4b913

set up PYNQU96 mem port 0 signals for coherency

Yaman Umuroglu · May 8, 2019, 11:23 PM UTC

3c65087786ed

go back to single memport TestCopy to prep for $-coherency tests

Yaman Umuroglu · May 8, 2019, 10:18 PM UTC

dfa2f63f2746

properly free up VerilatedTester in platform.cpp

Yaman Umuroglu · May 1, 2019, 2:54 PM UTC

8b337b466ada

[Characterization] call zsh explicitly to solve +x permission prb

Yaman Umuroglu · Apr 25, 2019, 2:39 PM UTC

899fbb51c8ec

[Characterization] export OHMYXILINX while running

Yaman Umuroglu · Apr 25, 2019, 2:31 PM UTC

7369a8877ac8

[Characterization] call omx from internal path

Yaman Umuroglu · Apr 25, 2019, 2:01 PM UTC

9a4dd648b513

[Characterization] add Characterization.scala from BISMO

Yaman Umuroglu · Apr 25, 2019, 1:45 PM UTC

36f481b40f03

[Characterization] add oh-my-xilinx as submodule

Yaman Umuroglu · Apr 25, 2019, 1:39 PM UTC

ec1c0dad7924

add fpgaPartMap to match board names to parts

Yaman Umuroglu · Apr 25, 2019, 1:13 PM UTC

07878375cbc0

add platform map entry for VerilatedTester

Yaman Umuroglu · Apr 4, 2019, 10:51 PM UTC

50b6e562478e

improved xlnkdriver for PYNQ: handle accelbuf with offset

Yaman Umuroglu · Feb 22, 2019, 12:54 AM UTC

2333824eb681

update ultra96 wrapper with 4 memory ports

Davide Conficconi · Jan 31, 2019, 11:34 AM UTC

8ebd83640972

add input queue to StreamDeinterleaverQueued, use FPGAQueue

Yaman Umuroglu · Jan 28, 2019, 12:24 AM UTC

d400793cc5db

bugfix for driver generation with no HLS blackboxes

Yaman Umuroglu · Nov 7, 2018, 11:59 PM UTC

71508834b9da

add own IO type for SerialToParallel

Yaman Umuroglu · Nov 7, 2018, 11:33 PM UTC

d340b0b9bc17

StreamCopy to broadcast to arbitrary number of streams in Seq

Yaman Umuroglu · Oct 31, 2018, 11:39 PM UTC

77317d40a0d4

expose used TemplatedHLSBlackBox params in generated driver

Yaman Umuroglu · Oct 29, 2018, 11:21 PM UTC

670ccea555f7

fix include path for generated HLS template defines

Yaman Umuroglu · Oct 29, 2018, 11:11 PM UTC

520b75884540

template arg generation for HLS blackboxes

Yaman Umuroglu · Oct 29, 2018, 9:55 PM UTC

d235f25a7daa

add TidbitsMakeUtils.makeHLSDependencies

Yaman Umuroglu · Oct 29, 2018, 9:03 PM UTC

dc3f2bbff31f

tracking function for HLSBlackBoxes

Yaman Umuroglu · Oct 29, 2018, 6:07 PM UTC

6c0f6cfeb2c2

use temporary dir as HLS project dir

Yaman Umuroglu · Oct 29, 2018, 5:39 PM UTC

26087eb611fe

add TidbitsHLSTools.hlsToVerilog

Yaman Umuroglu · Oct 29, 2018, 5:07 PM UTC

9b2de5776c69

add TemplatedHLSBlackBox for working with templated HLS

Yaman Umuroglu · Oct 27, 2018, 11:17 PM UTC

716215087545

omit date from accelerator signature generation

Yaman Umuroglu · Oct 24, 2018, 3:12 PM UTC

4fb240c86e07

vcd dump support in emulation

Yaman Umuroglu · Oct 22, 2018, 10:08 AM UTC

8796443befd8

fix Ultra96 CSR base address

Yaman Umuroglu · Oct 18, 2018, 9:06 AM UTC

07636bb17899

start adding PYNQU96Wrapper for PYNQ on Ultra-96

Yaman Umuroglu · Oct 17, 2018, 8:58 PM UTC

3a28a6856ce8

remove VerilatedTester debug print

Yaman Umuroglu · Oct 3, 2018, 10:51 PM UTC

8fef3585bb2f

change Verilator default path to match 3.916

Yaman Umuroglu · Oct 3, 2018, 10:48 PM UTC

d0f90e8a7058

64-byte aligned allocations in VerilatedTesterDriver

Yaman Umuroglu · Oct 3, 2018, 10:46 PM UTC

e475079884a0

Verilator emu: fix #mem words, generation target dir

Yaman Umuroglu · Oct 3, 2018, 10:35 PM UTC

97ff14ebe7a8

fix bug for >2 levels in index gen, improve testbench

Yaman Umuroglu · Sep 30, 2018, 11:32 PM UTC

a67d028b38bb

add AffineLoopNestIndGen and basic test, passing for 2d loops

Yaman Umuroglu · Sep 30, 2018, 11:26 PM UTC

e7a9a5c2ae02

remove old, broken tests

Yaman Umuroglu · Sep 28, 2018, 4:35 PM UTC

a1f2a5d74e7a

add a simple modulo counter

Yaman Umuroglu · Sep 28, 2018, 4:34 PM UTC

e7e3200a32f6

Merge branch for GenericSDAccel platform support

Yaman Umuroglu · Sep 7, 2018, 11:00 AM UTC

b347193d8fbe

also include VHDL sources in SDAccel package_ip

Yaman Umuroglu · Sep 6, 2018, 9:17 PM UTC

feb0fe3870b3