Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.
Added software-hardware perceptron learning to fpga-nn-api and various fixes
Kuronogard · Jun 10, 2017, 4:14 PM UTC
7be4561e405e
Fixes in fpga-nn-api - Writes/reads to/from perceptron seems to work now.
Kuronogard · Jun 9, 2017, 5:31 PM UTC
57326ca67187
Removed useless files from fpga-nn-api
Kuronogard · Jun 9, 2017, 5:31 PM UTC
4dd7fd4bdfbf
Fixes in perceptron
Kuronogard · Jun 9, 2017, 5:30 PM UTC
025d2635e64b
Fixes in uart and uart_echo
Kuronogard · Jun 9, 2017, 5:29 PM UTC
2a7641fa4ca1
Changed iceZUM alhambra perceptron from 16b to 8b precision
Kuronogard · Jun 9, 2017, 12:11 AM UTC
eb9e943c2f12
Deleted perceptron_top_tb and created testbenches for perceptrons configured in 16b and 8b precision
Kuronogard · Jun 9, 2017, 12:10 AM UTC
8637a96691c8
Modified perceptron so its precision is now parameterized
Kuronogard · Jun 9, 2017, 12:09 AM UTC
78f2ceb0aa0d
Created C api to access fpga-nn from outside the chip
Kuronogard · Jun 4, 2017, 8:12 AM UTC
35cba57dc840
Added constraint file support in xilinx workflow - Added master .ucf file for nexys2 board - Added .ucf file for perceptron project - Created nexys2 top file for perceptron project
Kuronogard · May 4, 2017, 11:12 AM UTC
4330a97180c6
Adapted the perceptron project for Spartan3e based boards - xilinx workflow added to build project - spartan3e synth and bitfile creation added to perceptron - adapted perceptron sources so they are compatible with xilinx's XST
Kuronogard · May 4, 2017, 9:47 AM UTC
e9920ee32f2c
Added an option to synthesize for xilinx 7-series fpgas
Kuronogard · Apr 29, 2017, 1:49 PM UTC
7e6ee0369ffc
Added perceptron schematic symbol as eagle library
Dennis · Apr 5, 2017, 2:22 PM UTC
1f88fe5bcdc7
Added some UART_rx documentation
Dennis · Apr 5, 2017, 2:20 PM UTC
1586fd595d45
Updated the output for 'make help'
Dennis · Apr 4, 2017, 4:57 PM UTC
f0e5bdeb59d8
The build system now allows to launch simulations, with wave configuration files under the sim_config directory
Dennis · Apr 4, 2017, 4:50 PM UTC
b29b408a5112
Build system now creates a timing analysis and shows a sumary of each generated report
Dennis · Apr 4, 2017, 4:08 PM UTC
98a46bb58857
Finished a first version of the perceptron (with no learning algorithm)
Dennis · Apr 4, 2017, 2:35 PM UTC
bd22407e51d8
Small fixes in UART
Dennis · Apr 4, 2017, 2:34 PM UTC
c6f6efaff768
Created module to manage simple communications with the perceptron. The implemented operations are: - Write weights (5 bytes: 1op + 4data), response (1 byte) - Write inputs (5 bytes: 1op + 4data), response (1 byte) - Read (1 byte), response (7 bytes: 1op + 6data)
Dennis · Mar 27, 2017, 5:40 PM UTC
b85400499707
Removed accidentaly commited temporary file
Dennis · Mar 22, 2017, 6:09 PM UTC
e106dac45e0a
Started perceptron top module for real FPGA implementation
Dennis · Mar 22, 2017, 6:07 PM UTC
e206aa94d943
Simple perceptron with threshold activation function finished
Dennis · Mar 22, 2017, 6:06 PM UTC
cd0f78b8c196
Changes in perceptron makefile to adapt the project current estandard
Dennis · Mar 22, 2017, 6:03 PM UTC
4ee6e3a868a8
Added note in UART header
Dennis · Mar 22, 2017, 6:02 PM UTC
3625b157f902
Created project uart_echo to test uart module - It receives a byte thought UART and inmediatly transmit it again. - UART baud rate at 9600. - Support for iceZUM alhambra board.
Dennis · Mar 21, 2017, 1:42 PM UTC
abaeb95ecc44
Created UART transmit and receive module as glue logic for uart_rx and uart_tx modules
Dennis · Mar 21, 2017, 12:34 PM UTC
960598ba2990
Added headers to testbench files
Dennis · Mar 21, 2017, 11:53 AM UTC
76fec0139c77
Fixed UART_rx baudrate syncronization
Dennis · Mar 21, 2017, 11:49 AM UTC
08a78352e0fe
Changes in UART_tx - baudrate and clock frequency are now configurables with parameters - Remodeled as Moore FSM
Dennis · Mar 21, 2017, 11:45 AM UTC
51c0726d1184
Removed waveform comfiguration file because it uses global paths
Dennis · Mar 21, 2017, 11:36 AM UTC
3bdb187ae0d2
Created 'simulation' directory for waveform configurations
Dennis · Mar 21, 2017, 10:03 AM UTC
b46ad10c197c
Created testbench for UART_rx module
Dennis · Mar 21, 2017, 10:02 AM UTC
032a68828d4b
Created receive module in UART project
Dennis · Mar 21, 2017, 10:01 AM UTC
36c56f6e87ec
Fixed typo in README.md
Dennis Pinto · Mar 20, 2017, 4:41 PM UTC
a14b3dafc5f2
Update README.md
Dennis Pinto · Mar 20, 2017, 4:40 PM UTC
27a1d064b3f8
Fixed errors in uart_tx
Dennis · Mar 15, 2017, 4:43 PM UTC
1178050e6909
Now the make command compile_all does not show the iverilog line
Dennis · Mar 15, 2017, 4:10 PM UTC
747de5c5b3b2
Added a help command to the main Makefile
Dennis · Mar 15, 2017, 4:06 PM UTC
1c183fbd00a0
Deleted innecesary files
Dennis · Mar 15, 2017, 3:53 PM UTC
dfcbd0e8bc23
Changes in Makefiles and sources - Added compilation to makefiles - Fixed errors in uart_tx so it now compiles - Created simple testbench for uart_tx
Dennis · Mar 15, 2017, 3:51 PM UTC
6abf73b1e1d8
Created UART project
Dennis · Mar 14, 2017, 3:58 PM UTC
ccbefbe41221
Basic project structure - Created the basic structure for fpga-nn projects - Created the base files for the "perceptron" project