chapter8 · FPGA-Application-Development-and-Simulation · master | ThingAtlas

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FPGA-Application-Development-and-Simulation

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Design files

Name	Storage	Size
.. / Parent directory
adpll.sv	Git	8.9 KB
am.sv	Git	8.4 KB
bpsk.sv	Git	5.7 KB
crc.sv

loywongadd missing ";" in memory.scala.b772052b4

Name

Storage

Size

.. / Parent directory

Git

8.9 KB

Git

8.4 KB

Git

5.7 KB

Git

1.8 KB

Git

4.9 KB

Git

419 B

Git

2.0 KB

Git

10.7 KB

Git

3.5 KB

sim_bpsk_wave.do

Git

6.3 KB

sim_car_rec_wave.do

Git

5.8 KB

sim_car_rec_wave2.do

Git

5.9 KB

Git

3.3 KB

sim_qam_iqth_wave.do

Git

3.4 KB

sim_qam_ova_wave.do

Git

4.0 KB

sim_qam_sj_wave.do

Git

3.5 KB

sim_qam_wave.do

Git

3.7 KB

Git

2 B

Git

91.7 KB

test_baseband.sv

Git

3.8 KB

test_bb_sys.cr.mti

Git

2.2 KB

test_bb_sys.mpf

Git

93.5 KB

test_bbsys_wave_detail.do

Git

2.6 KB

test_bbsys_wave.do

Git

1.6 KB

test_bpsk.cr.mti

Git

2 B

Git

91.7 KB

test_carrier_recovery.cr.mti

Git

1.2 KB

test_carrier_recovery.mpf

Git

91.7 KB

Git

997 B

Git

91.7 KB

test_qam16.cr.mti

Git

1.0 KB

Git

91.7 KB

Git

320.0 KB