Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.
add missing ";" in memory.scala.
loywong · Aug 18, 2026, 8:27 AM UTC
b772052b4780
1. add memory_readme.dio.svg.
loywong · Mar 3, 2026, 12:21 PM UTC
7aa5c64cfd1e
1. add memory_readme.dio.svg. 2. RAM modules now using underlying inline verilogHDL by default, including: ScFifo2 in scfifo.scala, DcFifo in cross_clock_domain.scala, StrFifo in str_common.scala. 3. add SyncReadMemRfByMem (using chisel3.Mem) in memory.scala. 4. add CleanResourcesListAnnotations() in gen_verilog.scala. 5. add DelayChainMem2 and DelayChainVariableLength in delay_chain.scala.
loywong · Mar 3, 2026, 12:04 PM UTC
e3962349f3d3
1. more detailed comment for Str(Id|Dest|User)Association in str_common.scala. 2. enlarge inner buffer in StrKeepRemover for elimiating possible thansfer bubble in some conditions.
loywong · Feb 3, 2026, 7:51 AM UTC
7523cbbf75a9
modified FixPoint in util.scala, now it supports chisel type derivation.
loywong · Jan 5, 2026, 2:10 PM UTC
d18b9eecb41c
add bitWidth arg for MemoryInitFiles.Write() in memory.scala.
loywong · Dec 3, 2025, 11:54 AM UTC
41d2b7c3f14f
1. add more utilities methods for FixPoint in util.scala. 2. fixed some bugs.
loywong · Nov 2, 2025, 10:13 AM UTC
142162a869a0
fixed a error equation in chisel/src/main/scala/loywong/cordic.md.
loywong · Oct 10, 2025, 1:23 PM UTC
8146a2e89a73
1. add more utilities for FixPoint in util.scala. 2. add more other utilities in util.scala.
loywong · Oct 10, 2025, 12:52 PM UTC
379f4421669d
add functions for getting/setting lowest and highest instance in class FixPoint in util.scala.
loywong · Sep 3, 2025, 7:23 AM UTC
48b896d1e715
1. fixed bugs: a) BitsUtil.asFixPoint and FixPoint.operator:= in util.scala. b) Constructors of StrActiveStage and StrPassiveStage in str_pipe_control.scala. 2. add verilog like shift "<<<" and ">>>" for SInt and FixPoint.
loywong · Aug 9, 2025, 8:36 AM UTC
f12ccf140e13
1. fixed some module naming bugs in memory.scala. 2. some minor modifications in util.scala.
loywong · Jun 11, 2025, 11:07 AM UTC
f361ce489144
add `chisel` dir, see `chisel/README.md`.
loywong · Jun 5, 2025, 4:41 PM UTC
85fd795a10f7
1. add dcfifo in chapter4. 2. add DelayChainMem3 (dynamic length) in chapter4. 3. add bridges for native fifo and stream in str_common.sv: str_snk_to_fifo_wr and fifo_rd_to_str_src.
loykylewong · Oct 18, 2024, 3:18 PM UTC
aa224c6e2fe7
1. removed all "word" dirs and "wlft*" files. 2. add cross_cd_trigger.sv in chapter4.
loywong · May 23, 2024, 2:50 PM UTC
771ce1587eb0
minor changes on code and README.
loywong · Jul 22, 2023, 9:27 AM UTC
7b275bf4c5ad
add HOLD mode in module InterpDeci in chapter7.
loywong · Jul 10, 2022, 9:58 AM UTC
e3cedf5d6d2c
Merge branch 'master' of github.com:loykylewong/FPGA-Application-Development-and-Simulation
loywong · May 26, 2022, 4:22 PM UTC
172ae3247463
fixed a bug in div_str. which may cause the remainder larger than or equal to the divisor and keep divisor * quotient + remainder = dividend.
loywong · May 26, 2022, 4:16 PM UTC
d265c83cb610
add license.md
loykylewong · Apr 9, 2022, 2:32 PM UTC
1fc96aac35f6
refine readme.
loywong · Apr 7, 2022, 8:35 AM UTC
c92ac4a67ca5
refine readme.
loywong · Apr 7, 2022, 8:31 AM UTC
1f871879a1f1
refine readme.
loywong · Apr 7, 2022, 8:24 AM UTC
413f832e2a28
add rst signal to some instances of scfifo and delaychainmem.
loywong · Apr 7, 2022, 8:14 AM UTC
0e82b1fdf683
1. Add reset signals to scfifo(s) and delay_chain_mem. Although I think one can add reset signals as needed when using them, I myself often forget. 2. Add some infrastructural stream modules. 3. Other minor changes.
loywong · Mar 20, 2022, 1:11 PM UTC
c29ab2119ded
1. add axi4lite_vivado_ip_template.sv, an expanded version of axi4lite_slave.sv, a good start point for writting self-defined ip in vivado.
loywong · Aug 17, 2021, 10:19 AM UTC
983338d69c3a
1. add axi4lite_vivado_ip_template.sv, a expanded version of axi4lite_slave.sv, a good start point for writting self-defined ip in vivado.
loywong · Aug 17, 2021, 10:19 AM UTC
aa234fa1cd76
1. add DelayChainMem2 which improved output behavior just like scfifo2. 2. add Pid2 which merged parameter TS into others. 2. add dual mode (rotation & vectoring) cordic. 3. add some fundamental modules for streaming.
loywong · Aug 17, 2021, 9:10 AM UTC
0aa2d4d4b31d
update errata.
loywong · Oct 21, 2020, 5:17 PM UTC
cdda35a313cb
alternative to DEF_FP_MUL by using "function" instead of "let".
loywong · Jun 25, 2020, 9:34 AM UTC
4da883e98a00
minor changes
loywong · Jun 25, 2020, 9:17 AM UTC
92c9ee396fef
.gitignore
loywong · Nov 8, 2019, 2:17 PM UTC
782ca256cceb
Add description about synthesizable in README.
loywong · Nov 8, 2019, 2:13 PM UTC
24f4876755ef
Fixed a minor bug of module Cordic the "arem" output of module Cordic was shifted 1 bit right to get the same fraction width of ain
loywong · Nov 8, 2019, 1:10 PM UTC
53a9d34480c5
修改了cic.sv中CicDownSampler模块的代码，以适应更大的抽取率。 Modified code for module CicDownSampler in cic.sv to accommodate larger decimation rate. 原代码不能用于(R*M)^N>=2^31的情况，最后的衰减系数attn的计算会溢出。 The original code can't be use when (R*M)^N >= 2^31, calculation for constant wire attn will overflow.
loywong · Oct 17, 2019, 9:55 AM UTC
fd277065aff8
修改了cic.sv中CicDownSampler模块的代码，以适应更大的抽取率。 Modified code for module CicDownSampler in cic.sv to accommodate larger decimation rate. 原代码不能用于(R*M)^N>=2^31的情况，localparam的计算会溢出。 The original code can't be use when (R*M)^N >= 2^31, calculation for localparams will overflow.