fmcw2

USB0_CAPLENGTH,0,8,CAPLENGTH,Indicates offset to add to the register base address at the beginning of the Operational Register,0x40,r
USB0_CAPLENGTH,8,16,HCIVERSION,BCD encoding of the EHCI revision number supported by this host controller,0x100,r
USB0_HCSPARAMS,0,4,N_PORTS,Number of downstream ports,0x1,r
USB0_HCSPARAMS,4,1,PPC,Port Power Control,0x1,r
USB0_HCSPARAMS,8,4,N_PCC,Number of Ports per Companion Controller,0x0,r
USB0_HCSPARAMS,12,4,N_CC,Number of Companion Controller,0x0,r
USB0_HCSPARAMS,16,1,PI,Port indicators,0x1,r
USB0_HCSPARAMS,20,4,N_PTT,Number of Ports per Transaction Translator,0x0,r
USB0_HCSPARAMS,24,4,N_TT,Number of Transaction Translators,0x0,r
USB0_HCCPARAMS,0,1,ADC,64-bit Addressing Capability,0,r
USB0_HCCPARAMS,1,1,PFL,Programmable Frame List Flag,1,r
USB0_HCCPARAMS,2,1,ASP,Asynchronous Schedule Park Capability,1,r
USB0_HCCPARAMS,4,4,IST,Isochronous Scheduling Threshold,0,r
USB0_HCCPARAMS,8,4,EECP,EHCI Extended Capabilities Pointer,0,r
USB0_DCCPARAMS,0,5,DEN,Device Endpoint Number,0x4,r
USB0_DCCPARAMS,7,1,DC,Device Capable,0x1,r
USB0_DCCPARAMS,8,1,HC,Host Capable,0x1,r
USB0_USBCMD_D,0,1,RS,Run/Stop,0,rw
USB0_USBCMD_D,1,1,RST,Controller reset,0,rw
USB0_USBCMD_D,13,1,SUTW,Setup trip wire,0,rw
USB0_USBCMD_D,14,1,ATDTW,Add dTD trip wire,0,rw
USB0_USBCMD_D,16,8,ITC,Interrupt threshold control,0x8,rw
USB0_USBCMD_H,0,1,RS,Run/Stop,0,rw
USB0_USBCMD_H,1,1,RST,Controller reset,0,rw
USB0_USBCMD_H,2,1,FS0,Bit 0 of the Frame List Size bits,0,
USB0_USBCMD_H,3,1,FS1,Bit 1 of the Frame List Size bits,0,
USB0_USBCMD_H,4,1,PSE,This bit controls whether the host controller skips processing the periodic schedule,0,rw
USB0_USBCMD_H,5,1,ASE,This bit controls whether the host controller skips processing the asynchronous schedule,0,rw
USB0_USBCMD_H,6,1,IAA,This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule,0,rw
USB0_USBCMD_H,8,2,ASP1_0,Asynchronous schedule park mode,0x3,rw
USB0_USBCMD_H,11,1,ASPE,Asynchronous Schedule Park Mode Enable,1,rw
USB0_USBCMD_H,15,1,FS2,Bit 2 of the Frame List Size bits,0,
USB0_USBCMD_H,16,8,ITC,Interrupt threshold control,0x8,rw
USB0_USBSTS_D,0,1,UI,USB interrupt,0,rwc
USB0_USBSTS_D,1,1,UEI,USB error interrupt,0,rwc
USB0_USBSTS_D,2,1,PCI,Port change detect,0,rwc
USB0_USBSTS_D,6,1,URI,USB reset received,0,rwc
USB0_USBSTS_D,7,1,SRI,SOF received,0,rwc
USB0_USBSTS_D,8,1,SLI,DCSuspend,0,rwc
USB0_USBSTS_D,16,1,NAKI,NAK interrupt bit,0,r
USB0_USBSTS_H,0,1,UI,USB interrupt,0,rwc
USB0_USBSTS_H,1,1,UEI,USB error interrupt,0,rwc
USB0_USBSTS_H,2,1,PCI,Port change detect,0,rwc
USB0_USBSTS_H,3,1,FRI,Frame list roll-over,0,rwc
USB0_USBSTS_H,5,1,AAI,Interrupt on async advance,0,rwc
USB0_USBSTS_H,7,1,SRI,SOF received,0,rwc
USB0_USBSTS_H,12,1,HCH,HCHalted,1,r
USB0_USBSTS_H,13,1,RCL,Reclamation,0,r
USB0_USBSTS_H,14,1,PS,Periodic schedule status,0,r
USB0_USBSTS_H,15,1,AS,Asynchronous schedule status,0,
USB0_USBSTS_H,18,1,UAI,USB host asynchronous interrupt (USBHSTASYNCINT),0,rwc
USB0_USBSTS_H,19,1,UPI,USB host periodic interrupt (USBHSTPERINT),0,rwc
USB0_USBINTR_D,0,1,UE,USB interrupt enable,0,rw
USB0_USBINTR_D,1,1,UEE,USB error interrupt enable,0,rw
USB0_USBINTR_D,2,1,PCE,Port change detect enable,0,rw
USB0_USBINTR_D,6,1,URE,USB reset enable,0,rw
USB0_USBINTR_D,7,1,SRE,SOF received enable,0,rw
USB0_USBINTR_D,8,1,SLE,Sleep enable,0,rw
USB0_USBINTR_D,16,1,NAKE,NAK interrupt enable,0,rw
USB0_USBINTR_H,0,1,UE,USB interrupt enable,0,rw
USB0_USBINTR_H,1,1,UEE,USB error interrupt enable,0,rw
USB0_USBINTR_H,2,1,PCE,Port change detect enable,0,rw
USB0_USBINTR_H,3,1,FRE,Frame list rollover enable,0,rw
USB0_USBINTR_H,5,1,AAE,Interrupt on asynchronous advance enable,0,rw
USB0_USBINTR_H,7,1,SRE,SOF received enable,0,
USB0_USBINTR_H,18,1,UAIE,USB host asynchronous interrupt enable,0,rw
USB0_USBINTR_H,19,1,UPIA,USB host periodic interrupt enable,0,rw
USB0_FRINDEX_D,0,3,FRINDEX2_0,Current micro frame number,,r
USB0_FRINDEX_D,3,11,FRINDEX13_3,Current frame number of the last frame transmitted,,r
USB0_FRINDEX_H,0,3,FRINDEX2_0,Current micro frame number,,rw
USB0_FRINDEX_H,3,10,FRINDEX12_3,Frame list current index,,rw
USB0_DEVICEADDR,24,1,USBADRA,Device address advance,0,
USB0_DEVICEADDR,25,7,USBADR,USB device address,0,rw
USB0_PERIODICLISTBASE,12,20,PERBASE31_12,Base Address (Low),,rw
USB0_ENDPOINTLISTADDR,11,21,EPBASE31_11,Endpoint list pointer (low),,rw
USB0_ASYNCLISTADDR,5,27,ASYBASE31_5,Link pointer (Low) LPL,,rw
USB0_TTCTRL,24,7,TTHA,Hub address when FS or LS device are connected directly,,rw
USB0_BURSTSIZE,0,8,RXPBURST,Programmable RX burst length,0x10,rw
USB0_BURSTSIZE,8,8,TXPBURST,Programmable TX burst length,0x10,rw
USB0_TXFILLTUNING,0,8,TXSCHOH,FIFO burst threshold,0x2,rw
USB0_TXFILLTUNING,8,5,TXSCHEATLTH,Scheduler health counter,0x0,rw
USB0_TXFILLTUNING,16,6,TXFIFOTHRES,Scheduler overhead,0x0,rw
USB0_BINTERVAL,0,4,BINT,bInterval value,0x00,rw
USB0_ENDPTNAK,0,6,EPRN,Rx endpoint NAK,0x00,rwc
USB0_ENDPTNAK,16,6,EPTN,Tx endpoint NAK,0x00,rwc
USB0_ENDPTNAKEN,0,6,EPRNE,Rx endpoint NAK enable,0x00,rw
USB0_ENDPTNAKEN,16,6,EPTNE,Tx endpoint NAK,0x00,rw
USB0_PORTSC1_D,0,1,CCS,Current connect status,0,r
USB0_PORTSC1_D,2,1,PE,Port enable,1,r
USB0_PORTSC1_D,3,1,PEC,Port enable/disable change,0,r
USB0_PORTSC1_D,6,1,FPR,Force port resume,0,rw
USB0_PORTSC1_D,7,1,SUSP,Suspend,0,r
USB0_PORTSC1_D,8,1,PR,Port reset,0,r
USB0_PORTSC1_D,9,1,HSP,High-speed status,0,r
USB0_PORTSC1_D,14,2,PIC1_0,Port indicator control,0,rw
USB0_PORTSC1_D,16,4,PTC3_0,Port test control,0,rw
USB0_PORTSC1_D,23,1,PHCD,PHY low power suspend - clock disable (PLPSCD),0,rw
USB0_PORTSC1_D,24,1,PFSC,Port force full speed connect,0,rw
USB0_PORTSC1_D,26,2,PSPD,Port speed,0,r
USB0_PORTSC1_H,0,1,CCS,Current connect status,0,rwc
USB0_PORTSC1_H,1,1,CSC,Connect status change,0,rwc
USB0_PORTSC1_H,2,1,PE,Port enable,0,rw
USB0_PORTSC1_H,3,1,PEC,Port disable/enable change,0,rwc
USB0_PORTSC1_H,4,1,OCA,Over-current active,0,r
USB0_PORTSC1_H,5,1,OCC,Over-current change,0,rwc
USB0_PORTSC1_H,6,1,FPR,Force port resume,0,rw
USB0_PORTSC1_H,7,1,SUSP,Suspend,0,rw
USB0_PORTSC1_H,8,1,PR,Port reset,0,rw
USB0_PORTSC1_H,9,1,HSP,High-speed status,0,r
USB0_PORTSC1_H,10,2,LS,Line status,0x3,r
USB0_PORTSC1_H,12,1,PP,Port power control,0,rw
USB0_PORTSC1_H,14,2,PIC1_0,Port indicator control,0,rw
USB0_PORTSC1_H,16,4,PTC3_0,Port test control,0,rw
USB0_PORTSC1_H,20,1,WKCN,Wake on connect enable (WKCNNT_E),0,rw
USB0_PORTSC1_H,21,1,WKDC,Wake on disconnect enable (WKDSCNNT_E),0,rw
USB0_PORTSC1_H,22,1,WKOC,Wake on over-current enable (WKOC_E),0,rw
USB0_PORTSC1_H,23,1,PHCD,PHY low power suspend - clock disable (PLPSCD),0,rw
USB0_PORTSC1_H,24,1,PFSC,Port force full speed connect,0,rw
USB0_PORTSC1_H,26,2,PSPD,Port speed,0,r
USB0_OTGSC,0,1,VD,VBUS_Discharge,0,rw
USB0_OTGSC,1,1,VC,VBUS_Charge,0,rw
USB0_OTGSC,2,1,HAAR,Hardware assist auto_reset,0,rw
USB0_OTGSC,3,1,OT,OTG termination,0,rw
USB0_OTGSC,4,1,DP,Data pulsing,0,rw
USB0_OTGSC,5,1,IDPU,ID pull-up,1,rw
USB0_OTGSC,6,1,HADP,Hardware assist data pulse,0,rw
USB0_OTGSC,7,1,HABA,Hardware assist B-disconnect to A-connect,0,rw
USB0_OTGSC,8,1,ID,USB ID,0,r
USB0_OTGSC,9,1,AVV,A-VBUS valid,0,r
USB0_OTGSC,10,1,ASV,A-session valid,0,r
USB0_OTGSC,11,1,BSV,B-session valid,0,r
USB0_OTGSC,12,1,BSE,B-session end,0,r
USB0_OTGSC,13,1,MS1T,1 millisecond timer toggle,0,r
USB0_OTGSC,14,1,DPS,Data bus pulsing status,0,r
USB0_OTGSC,16,1,IDIS,USB ID interrupt status,0,rwc
USB0_OTGSC,17,1,AVVIS,A-VBUS valid interrupt status,0,rwc
USB0_OTGSC,18,1,ASVIS,A-Session valid interrupt status,0,rwc
USB0_OTGSC,19,1,BSVIS,B-Session valid interrupt status,0,rwc
USB0_OTGSC,20,1,BSEIS,B-Session end interrupt status,0,rwc
USB0_OTGSC,21,1,MS1S,1 millisecond timer interrupt status,0,rwc
USB0_OTGSC,22,1,DPIS,Data pulse interrupt status,0,rwc
USB0_OTGSC,24,1,IDIE,USB ID interrupt enable,0,rw
USB0_OTGSC,25,1,AVVIE,A-VBUS valid interrupt enable,0,rw
USB0_OTGSC,26,1,ASVIE,A-session valid interrupt enable,0,rw
USB0_OTGSC,27,1,BSVIE,B-session valid interrupt enable,0,rw
USB0_OTGSC,28,1,BSEIE,B-session end interrupt enable,0,rw
USB0_OTGSC,29,1,MS1E,1 millisecond timer interrupt enable,0,rw
USB0_OTGSC,30,1,DPIE,Data pulse interrupt enable,0,rw
USB0_USBMODE_D,0,2,CM1_0,Controller mode,0,rwo
USB0_USBMODE_D,2,1,ES,Endian select,0,rw
USB0_USBMODE_D,3,1,SLOM,Setup Lockout mode,0,rw
USB0_USBMODE_D,4,1,SDIS,Setup Lockout mode,0,rw
USB0_USBMODE_H,0,2,CM,Controller mode,0,rwo
USB0_USBMODE_H,2,1,ES,Endian select,0,rw
USB0_USBMODE_H,4,1,SDIS,Stream disable mode,0,rw
USB0_USBMODE_H,5,1,VBPS,VBUS power select,0,rwo
USB0_ENDPTSETUPSTAT,0,6,ENDPTSETUPSTAT,Setup endpoint status for logical endpoints 0 to 5,0,rwc
USB0_ENDPTPRIME,0,6,PERB,Prime endpoint receive buffer for physical OUT endpoints 5 to 0,0,rws
USB0_ENDPTPRIME,16,6,PETB,Prime endpoint transmit buffer for physical IN endpoints 5 to 0,0,rws
USB0_ENDPTFLUSH,0,6,FERB,Flush endpoint receive buffer for physical OUT endpoints 5 to 0,0,rwc
USB0_ENDPTFLUSH,16,6,FETB,Flush endpoint transmit buffer for physical IN endpoints 5 to 0,0,rwc
USB0_ENDPTSTAT,0,6,ERBR,Endpoint receive buffer ready for physical OUT endpoints 5 to 0,0,r
USB0_ENDPTSTAT,16,6,ETBR,Endpoint transmit buffer ready for physical IN endpoints 3 to 0,0,r
USB0_ENDPTCOMPLETE,0,6,ERCE,Endpoint receive complete event for physical OUT endpoints 5 to 0,0,rwc
USB0_ENDPTCOMPLETE,16,6,ETCE,Endpoint transmit complete event for physical IN endpoints 5 to 0,0,rwc
USB0_ENDPTCTRL0,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL0,2,2,RXT1_0,Endpoint type,0,rw
USB0_ENDPTCTRL0,7,1,RXE,Rx endpoint enable,1,r
USB0_ENDPTCTRL0,16,1,TXS,Tx endpoint stall,,rw
USB0_ENDPTCTRL0,18,2,TXT1_0,Endpoint type,0,r
USB0_ENDPTCTRL0,23,1,TXE,Tx endpoint enable,1,r
USB0_ENDPTCTRL1,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL1,2,2,RXT,Endpoint type,0,rw
USB0_ENDPTCTRL1,5,1,RXI,Rx data toggle inhibit,0,rw
USB0_ENDPTCTRL1,6,1,RXR,Rx data toggle reset,0,ws
USB0_ENDPTCTRL1,7,1,RXE,Rx endpoint enable,0,rw
USB0_ENDPTCTRL1,16,1,TXS,Tx endpoint stall,0,rw
USB0_ENDPTCTRL1,18,2,TXT1_0,Tx Endpoint type,0,r
USB0_ENDPTCTRL1,21,1,TXI,Tx data toggle inhibit,0,rw
USB0_ENDPTCTRL1,22,1,TXR,Tx data toggle reset,1,ws
USB0_ENDPTCTRL1,23,1,TXE,Tx endpoint enable,0,r
USB0_ENDPTCTRL2,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL2,2,2,RXT,Endpoint type,0,rw
USB0_ENDPTCTRL2,5,1,RXI,Rx data toggle inhibit,0,rw
USB0_ENDPTCTRL2,6,1,RXR,Rx data toggle reset,0,ws
USB0_ENDPTCTRL2,7,1,RXE,Rx endpoint enable,0,rw
USB0_ENDPTCTRL2,16,1,TXS,Tx endpoint stall,0,rw
USB0_ENDPTCTRL2,18,2,TXT1_0,Tx Endpoint type,0,r
USB0_ENDPTCTRL2,21,1,TXI,Tx data toggle inhibit,0,rw
USB0_ENDPTCTRL2,22,1,TXR,Tx data toggle reset,1,ws
USB0_ENDPTCTRL2,23,1,TXE,Tx endpoint enable,0,r
USB0_ENDPTCTRL3,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL3,2,2,RXT,Endpoint type,0,rw
USB0_ENDPTCTRL3,5,1,RXI,Rx data toggle inhibit,0,rw
USB0_ENDPTCTRL3,6,1,RXR,Rx data toggle reset,0,ws
USB0_ENDPTCTRL3,7,1,RXE,Rx endpoint enable,0,rw
USB0_ENDPTCTRL3,16,1,TXS,Tx endpoint stall,0,rw
USB0_ENDPTCTRL3,18,2,TXT1_0,Tx Endpoint type,0,r
USB0_ENDPTCTRL3,21,1,TXI,Tx data toggle inhibit,0,rw
USB0_ENDPTCTRL3,22,1,TXR,Tx data toggle reset,1,ws
USB0_ENDPTCTRL3,23,1,TXE,Tx endpoint enable,0,r
USB0_ENDPTCTRL4,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL4,2,2,RXT,Endpoint type,0,rw
USB0_ENDPTCTRL4,5,1,RXI,Rx data toggle inhibit,0,rw
USB0_ENDPTCTRL4,6,1,RXR,Rx data toggle reset,0,ws
USB0_ENDPTCTRL4,7,1,RXE,Rx endpoint enable,0,rw
USB0_ENDPTCTRL4,16,1,TXS,Tx endpoint stall,0,rw
USB0_ENDPTCTRL4,18,2,TXT1_0,Tx Endpoint type,0,r
USB0_ENDPTCTRL4,21,1,TXI,Tx data toggle inhibit,0,rw
USB0_ENDPTCTRL4,22,1,TXR,Tx data toggle reset,1,ws
USB0_ENDPTCTRL4,23,1,TXE,Tx endpoint enable,0,r
USB0_ENDPTCTRL5,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL5,2,2,RXT,Endpoint type,0,rw
USB0_ENDPTCTRL5,5,1,RXI,Rx data toggle inhibit,0,rw
USB0_ENDPTCTRL5,6,1,RXR,Rx data toggle reset,0,ws
USB0_ENDPTCTRL5,7,1,RXE,Rx endpoint enable,0,rw
USB0_ENDPTCTRL5,16,1,TXS,Tx endpoint stall,0,rw
USB0_ENDPTCTRL5,18,2,TXT1_0,Tx Endpoint type,0,r
USB0_ENDPTCTRL5,21,1,TXI,Tx data toggle inhibit,0,rw
USB0_ENDPTCTRL5,22,1,TXR,Tx data toggle reset,1,ws
USB0_ENDPTCTRL5,23,1,TXE,Tx endpoint enable,0,r