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<title>DIY Logging Volt/Ampmeter: STM32F103C8T6_powermeter-interface/Drivers/CMSIS/Include/core_cm0.h Source File</title>
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<div class="title">core_cm0.h</div> </div>
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<a href="core__cm0_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span> <span class="comment">/**************************************************************************/</span><span class="comment">/**</span></div>
<div class="line"><a name="l00002"></a><span class="lineno"> 2</span> <span class="comment"> * @file core_cm0.h</span></div>
<div class="line"><a name="l00003"></a><span class="lineno"> 3</span> <span class="comment"> * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File</span></div>
<div class="line"><a name="l00004"></a><span class="lineno"> 4</span> <span class="comment"> * @version V5.0.5</span></div>
<div class="line"><a name="l00005"></a><span class="lineno"> 5</span> <span class="comment"> * @date 28. May 2018</span></div>
<div class="line"><a name="l00006"></a><span class="lineno"> 6</span> <span class="comment"> ******************************************************************************/</span></div>
<div class="line"><a name="l00007"></a><span class="lineno"> 7</span> <span class="comment">/*</span></div>
<div class="line"><a name="l00008"></a><span class="lineno"> 8</span> <span class="comment"> * Copyright (c) 2009-2018 Arm Limited. All rights reserved.</span></div>
<div class="line"><a name="l00009"></a><span class="lineno"> 9</span> <span class="comment"> *</span></div>
<div class="line"><a name="l00010"></a><span class="lineno"> 10</span> <span class="comment"> * SPDX-License-Identifier: Apache-2.0</span></div>
<div class="line"><a name="l00011"></a><span class="lineno"> 11</span> <span class="comment"> *</span></div>
<div class="line"><a name="l00012"></a><span class="lineno"> 12</span> <span class="comment"> * Licensed under the Apache License, Version 2.0 (the License); you may</span></div>
<div class="line"><a name="l00013"></a><span class="lineno"> 13</span> <span class="comment"> * not use this file except in compliance with the License.</span></div>
<div class="line"><a name="l00014"></a><span class="lineno"> 14</span> <span class="comment"> * You may obtain a copy of the License at</span></div>
<div class="line"><a name="l00015"></a><span class="lineno"> 15</span> <span class="comment"> *</span></div>
<div class="line"><a name="l00016"></a><span class="lineno"> 16</span> <span class="comment"> * www.apache.org/licenses/LICENSE-2.0</span></div>
<div class="line"><a name="l00017"></a><span class="lineno"> 17</span> <span class="comment"> *</span></div>
<div class="line"><a name="l00018"></a><span class="lineno"> 18</span> <span class="comment"> * Unless required by applicable law or agreed to in writing, software</span></div>
<div class="line"><a name="l00019"></a><span class="lineno"> 19</span> <span class="comment"> * distributed under the License is distributed on an AS IS BASIS, WITHOUT</span></div>
<div class="line"><a name="l00020"></a><span class="lineno"> 20</span> <span class="comment"> * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.</span></div>
<div class="line"><a name="l00021"></a><span class="lineno"> 21</span> <span class="comment"> * See the License for the specific language governing permissions and</span></div>
<div class="line"><a name="l00022"></a><span class="lineno"> 22</span> <span class="comment"> * limitations under the License.</span></div>
<div class="line"><a name="l00023"></a><span class="lineno"> 23</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00024"></a><span class="lineno"> 24</span>  </div>
<div class="line"><a name="l00025"></a><span class="lineno"> 25</span> <span class="preprocessor">#if defined ( __ICCARM__ )</span></div>
<div class="line"><a name="l00026"></a><span class="lineno"> 26</span> <span class="preprocessor"> #pragma system_include </span><span class="comment">/* treat file as system include file for MISRA check */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00027"></a><span class="lineno"> 27</span> <span class="preprocessor">#elif defined (__clang__)</span></div>
<div class="line"><a name="l00028"></a><span class="lineno"> 28</span> <span class="preprocessor"> #pragma clang system_header </span><span class="comment">/* treat file as system include file */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00029"></a><span class="lineno"> 29</span> <span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00030"></a><span class="lineno"> 30</span>  </div>
<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#ifndef __CORE_CM0_H_GENERIC</span></div>
<div class="line"><a name="l00032"></a><span class="lineno"><a class="line" href="core__cm0_8h.html#a1c7b83f58ef7b4d6b5f50ec1e294b34e"> 32</a></span> <span class="preprocessor">#define __CORE_CM0_H_GENERIC</span></div>
<div class="line"><a name="l00033"></a><span class="lineno"> 33</span>  </div>
<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor">#include <stdint.h></span></div>
<div class="line"><a name="l00035"></a><span class="lineno"> 35</span>  </div>
<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor">#ifdef __cplusplus</span></div>
<div class="line"><a name="l00037"></a><span class="lineno"> 37</span>  <span class="keyword">extern</span> <span class="stringliteral">"C"</span> {</div>
<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="comment"></span> </div>
<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> <span class="comment"> \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions</span></div>
<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="comment"> CMSIS violates the following MISRA-C:2004 rules:</span></div>
<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="comment"></span> </div>
<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="comment"> \li Required Rule 8.5, object/function definition in header file.<br></span></div>
<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> <span class="comment"> Function definitions in header files are used to allow 'inlining'.</span></div>
<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="comment"></span> </div>
<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="comment"> \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br></span></div>
<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="comment"> Unions are used for effective representation of core registers.</span></div>
<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="comment"></span> </div>
<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="comment"> \li Advisory Rule 19.7, Function-like macro defined.<br></span></div>
<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> <span class="comment"> Function-like macros are used to allow more efficient code.</span></div>
<div class="line"><a name="l00052"></a><span class="lineno"> 52</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00053"></a><span class="lineno"> 53</span>  </div>
<div class="line"><a name="l00054"></a><span class="lineno"> 54</span>  </div>
<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="comment">/*******************************************************************************</span></div>
<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="comment"> * CMSIS definitions</span></div>
<div class="line"><a name="l00057"></a><span class="lineno"> 57</span> <span class="comment"> ******************************************************************************/</span><span class="comment"></span></div>
<div class="line"><a name="l00058"></a><span class="lineno"> 58</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00059"></a><span class="lineno"> 59</span> <span class="comment"> \ingroup Cortex_M0</span></div>
<div class="line"><a name="l00060"></a><span class="lineno"> 60</span> <span class="comment"> @{</span></div>
<div class="line"><a name="l00061"></a><span class="lineno"> 61</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00062"></a><span class="lineno"> 62</span>  </div>
<div class="line"><a name="l00063"></a><span class="lineno"> 63</span> <span class="preprocessor">#include "<a class="code" href="cmsis__version_8h.html">cmsis_version.h</a>"</span></div>
<div class="line"><a name="l00064"></a><span class="lineno"> 64</span>  </div>
<div class="line"><a name="l00065"></a><span class="lineno"> 65</span> <span class="comment">/* CMSIS CM0 definitions */</span></div>
<div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="core__cm0_8h.html#acd01bf0a654a7f15f606593aa636bc72"> 66</a></span> <span class="preprocessor">#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) </span><span class="comment">/*!< \deprecated [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00067"></a><span class="lineno"><a class="line" href="core__cm0_8h.html#ab6a85b0d3b2fbcfb62003006ece175cc"> 67</a></span> <span class="preprocessor">#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) </span><span class="comment">/*!< \deprecated [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="core__cm0_8h.html#af233a7b7b2818cc6194e7a9386faccd8"> 68</a></span> <span class="preprocessor">#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \</span></div>
<div class="line"><a name="l00069"></a><span class="lineno"> 69</span> <span class="preprocessor"> __CM0_CMSIS_VERSION_SUB ) </span><span class="comment">/*!< \deprecated CMSIS HAL version number */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00070"></a><span class="lineno"> 70</span>  </div>
<div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="core__cm0_8h.html#a63ea62503c88acab19fcf3d5743009e3"> 71</a></span> <span class="preprocessor">#define __CORTEX_M (0U) </span><span class="comment">/*!< Cortex-M Core */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00072"></a><span class="lineno"> 72</span> <span class="comment"></span> </div>
<div class="line"><a name="l00073"></a><span class="lineno"> 73</span> <span class="comment">/** __FPU_USED indicates whether an FPU is used or not.</span></div>
<div class="line"><a name="l00074"></a><span class="lineno"> 74</span> <span class="comment"> This core does not support an FPU at all</span></div>
<div class="line"><a name="l00075"></a><span class="lineno"> 75</span> <span class="comment">*/</span></div>
<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="core__cm0_8h.html#aa167d0f532a7c2b2e3a6395db2fa0776"> 76</a></span> <span class="preprocessor">#define __FPU_USED 0U</span></div>
<div class="line"><a name="l00077"></a><span class="lineno"> 77</span>  </div>
<div class="line"><a name="l00078"></a><span class="lineno"> 78</span> <span class="preprocessor">#if defined ( __CC_ARM )</span></div>
<div class="line"><a name="l00079"></a><span class="lineno"> 79</span> <span class="preprocessor"> #if defined __TARGET_FPU_VFP</span></div>
<div class="line"><a name="l00080"></a><span class="lineno"> 80</span> <span class="preprocessor"> #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"</span></div>
<div class="line"><a name="l00081"></a><span class="lineno"> 81</span> <span class="preprocessor"> #endif</span></div>
<div class="line"><a name="l00082"></a><span class="lineno"> 82</span>  </div>
<div class="line"><a name="l00083"></a><span class="lineno"> 83</span> <span class="preprocessor">#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)</span></div>
<div class="line"><a name="l00084"></a><span class="lineno"> 84</span> <span class="preprocessor"> #if defined __ARM_PCS_VFP</span></div>
<div class="line"><a name="l00085"></a><span class="lineno"> 85</span> <span class="preprocessor"> #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"</span></div>
<div class="line"><a name="l00086"></a><span class="lineno"> 86</span> <span class="preprocessor"> #endif</span></div>
<div class="line"><a name="l00087"></a><span class="lineno"> 87</span>  </div>
<div class="line"><a name="l00088"></a><span class="lineno"> 88</span> <span class="preprocessor">#elif defined ( __GNUC__ )</span></div>
<div class="line"><a name="l00089"></a><span class="lineno"> 89</span> <span class="preprocessor"> #if defined (__VFP_FP__) && !defined(__SOFTFP__)</span></div>
<div class="line"><a name="l00090"></a><span class="lineno"> 90</span> <span class="preprocessor"> #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"</span></div>
<div class="line"><a name="l00091"></a><span class="lineno"> 91</span> <span class="preprocessor"> #endif</span></div>
<div class="line"><a name="l00092"></a><span class="lineno"> 92</span>  </div>
<div class="line"><a name="l00093"></a><span class="lineno"> 93</span> <span class="preprocessor">#elif defined ( __ICCARM__ )</span></div>
<div class="line"><a name="l00094"></a><span class="lineno"> 94</span> <span class="preprocessor"> #if defined __ARMVFP__</span></div>
<div class="line"><a name="l00095"></a><span class="lineno"> 95</span> <span class="preprocessor"> #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"</span></div>
<div class="line"><a name="l00096"></a><span class="lineno"> 96</span> <span class="preprocessor"> #endif</span></div>
<div class="line"><a name="l00097"></a><span class="lineno"> 97</span>  </div>
<div class="line"><a name="l00098"></a><span class="lineno"> 98</span> <span class="preprocessor">#elif defined ( __TI_ARM__ )</span></div>
<div class="line"><a name="l00099"></a><span class="lineno"> 99</span> <span class="preprocessor"> #if defined __TI_VFP_SUPPORT__</span></div>
<div class="line"><a name="l00100"></a><span class="lineno"> 100</span> <span class="preprocessor"> #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"</span></div>
<div class="line"><a name="l00101"></a><span class="lineno"> 101</span> <span class="preprocessor"> #endif</span></div>
<div class="line"><a name="l00102"></a><span class="lineno"> 102</span>  </div>
<div class="line"><a name="l00103"></a><span class="lineno"> 103</span> <span class="preprocessor">#elif defined ( __TASKING__ )</span></div>
<div class="line"><a name="l00104"></a><span class="lineno"> 104</span> <span class="preprocessor"> #if defined __FPU_VFP__</span></div>
<div class="line"><a name="l00105"></a><span class="lineno"> 105</span> <span class="preprocessor"> #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"</span></div>
<div class="line"><a name="l00106"></a><span class="lineno"> 106</span> <span class="preprocessor"> #endif</span></div>
<div class="line"><a name="l00107"></a><span class="lineno"> 107</span>  </div>
<div class="line"><a name="l00108"></a><span class="lineno"> 108</span> <span class="preprocessor">#elif defined ( __CSMC__ )</span></div>
<div class="line"><a name="l00109"></a><span class="lineno"> 109</span> <span class="preprocessor"> #if ( __CSMC__ & 0x400U)</span></div>
<div class="line"><a name="l00110"></a><span class="lineno"> 110</span> <span class="preprocessor"> #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"</span></div>
<div class="line"><a name="l00111"></a><span class="lineno"> 111</span> <span class="preprocessor"> #endif</span></div>
<div class="line"><a name="l00112"></a><span class="lineno"> 112</span>  </div>
<div class="line"><a name="l00113"></a><span class="lineno"> 113</span> <span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00114"></a><span class="lineno"> 114</span>  </div>
<div class="line"><a name="l00115"></a><span class="lineno"> 115</span> <span class="preprocessor">#include "<a class="code" href="cmsis__compiler_8h.html">cmsis_compiler.h</a>"</span> <span class="comment">/* CMSIS compiler specific defines */</span></div>
<div class="line"><a name="l00116"></a><span class="lineno"> 116</span>  </div>
<div class="line"><a name="l00117"></a><span class="lineno"> 117</span>  </div>
<div class="line"><a name="l00118"></a><span class="lineno"> 118</span> <span class="preprocessor">#ifdef __cplusplus</span></div>
<div class="line"><a name="l00119"></a><span class="lineno"> 119</span> }</div>
<div class="line"><a name="l00120"></a><span class="lineno"> 120</span> <span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00121"></a><span class="lineno"> 121</span>  </div>
<div class="line"><a name="l00122"></a><span class="lineno"> 122</span> <span class="preprocessor">#endif </span><span class="comment">/* __CORE_CM0_H_GENERIC */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00123"></a><span class="lineno"> 123</span>  </div>
<div class="line"><a name="l00124"></a><span class="lineno"> 124</span> <span class="preprocessor">#ifndef __CMSIS_GENERIC</span></div>
<div class="line"><a name="l00125"></a><span class="lineno"> 125</span>  </div>
<div class="line"><a name="l00126"></a><span class="lineno"> 126</span> <span class="preprocessor">#ifndef __CORE_CM0_H_DEPENDANT</span></div>
<div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="core__cm0_8h.html#ac1e2acb34ba7f2543bcb2249bead4aee"> 127</a></span> <span class="preprocessor">#define __CORE_CM0_H_DEPENDANT</span></div>
<div class="line"><a name="l00128"></a><span class="lineno"> 128</span>  </div>
<div class="line"><a name="l00129"></a><span class="lineno"> 129</span> <span class="preprocessor">#ifdef __cplusplus</span></div>
<div class="line"><a name="l00130"></a><span class="lineno"> 130</span>  <span class="keyword">extern</span> <span class="stringliteral">"C"</span> {</div>
<div class="line"><a name="l00131"></a><span class="lineno"> 131</span> <span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00132"></a><span class="lineno"> 132</span>  </div>
<div class="line"><a name="l00133"></a><span class="lineno"> 133</span> <span class="comment">/* check device defines and use defaults */</span></div>
<div class="line"><a name="l00134"></a><span class="lineno"> 134</span> <span class="preprocessor">#if defined __CHECK_DEVICE_DEFINES</span></div>
<div class="line"><a name="l00135"></a><span class="lineno"> 135</span> <span class="preprocessor"> #ifndef __CM0_REV</span></div>
<div class="line"><a name="l00136"></a><span class="lineno"> 136</span> <span class="preprocessor"> #define __CM0_REV 0x0000U</span></div>
<div class="line"><a name="l00137"></a><span class="lineno"> 137</span> <span class="preprocessor"> #warning "__CM0_REV not defined in device header file; using default!"</span></div>
<div class="line"><a name="l00138"></a><span class="lineno"> 138</span> <span class="preprocessor"> #endif</span></div>
<div class="line"><a name="l00139"></a><span class="lineno"> 139</span>  </div>
<div class="line"><a name="l00140"></a><span class="lineno"> 140</span> <span class="preprocessor"> #ifndef __NVIC_PRIO_BITS</span></div>
<div class="line"><a name="l00141"></a><span class="lineno"> 141</span> <span class="preprocessor"> #define __NVIC_PRIO_BITS 2U</span></div>
<div class="line"><a name="l00142"></a><span class="lineno"> 142</span> <span class="preprocessor"> #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"</span></div>
<div class="line"><a name="l00143"></a><span class="lineno"> 143</span> <span class="preprocessor"> #endif</span></div>
<div class="line"><a name="l00144"></a><span class="lineno"> 144</span>  </div>
<div class="line"><a name="l00145"></a><span class="lineno"> 145</span> <span class="preprocessor"> #ifndef __Vendor_SysTickConfig</span></div>
<div class="line"><a name="l00146"></a><span class="lineno"> 146</span> <span class="preprocessor"> #define __Vendor_SysTickConfig 0U</span></div>
<div class="line"><a name="l00147"></a><span class="lineno"> 147</span> <span class="preprocessor"> #warning "__Vendor_SysTickConfig not defined in device header file; using default!"</span></div>
<div class="line"><a name="l00148"></a><span class="lineno"> 148</span> <span class="preprocessor"> #endif</span></div>
<div class="line"><a name="l00149"></a><span class="lineno"> 149</span> <span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00150"></a><span class="lineno"> 150</span>  </div>
<div class="line"><a name="l00151"></a><span class="lineno"> 151</span> <span class="comment">/* IO definitions (access restrictions to peripheral registers) */</span><span class="comment"></span></div>
<div class="line"><a name="l00152"></a><span class="lineno"> 152</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00153"></a><span class="lineno"> 153</span> <span class="comment"> \defgroup CMSIS_glob_defs CMSIS Global Defines</span></div>
<div class="line"><a name="l00154"></a><span class="lineno"> 154</span> <span class="comment"></span> </div>
<div class="line"><a name="l00155"></a><span class="lineno"> 155</span> <span class="comment"> <strong>IO Type Qualifiers</strong> are used</span></div>
<div class="line"><a name="l00156"></a><span class="lineno"> 156</span> <span class="comment"> \li to specify the access to peripheral variables.</span></div>
<div class="line"><a name="l00157"></a><span class="lineno"> 157</span> <span class="comment"> \li for automatic generation of peripheral register debug information.</span></div>
<div class="line"><a name="l00158"></a><span class="lineno"> 158</span> <span class="comment">*/</span></div>
<div class="line"><a name="l00159"></a><span class="lineno"> 159</span> <span class="preprocessor">#ifdef __cplusplus</span></div>
<div class="line"><a name="l00160"></a><span class="lineno"> 160</span> <span class="preprocessor"> #define __I volatile </span><span class="comment">/*!< Defines 'read only' permissions */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00161"></a><span class="lineno"> 161</span> <span class="preprocessor">#else</span></div>
<div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="core__cm0_8h.html#af63697ed9952cc71e1225efe205f6cd3"> 162</a></span> <span class="preprocessor"> #define __I volatile const </span><span class="comment">/*!< Defines 'read only' permissions */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00163"></a><span class="lineno"> 163</span> <span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="core__cm0_8h.html#a7e25d9380f9ef903923964322e71f2f6"> 164</a></span> <span class="preprocessor">#define __O volatile </span><span class="comment">/*!< Defines 'write only' permissions */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="core__cm0_8h.html#aec43007d9998a0a0e01faede4133d6be"> 165</a></span> <span class="preprocessor">#define __IO volatile </span><span class="comment">/*!< Defines 'read / write' permissions */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00166"></a><span class="lineno"> 166</span>  </div>
<div class="line"><a name="l00167"></a><span class="lineno"> 167</span> <span class="comment">/* following defines should be used for structure members */</span></div>
<div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="core__cm0_8h.html#a4cc1649793116d7c2d8afce7a4ffce43"> 168</a></span> <span class="preprocessor">#define __IM volatile const </span><span class="comment">/*! Defines 'read only' structure member permissions */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="core__cm0_8h.html#a0ea2009ed8fd9ef35b48708280fdb758"> 169</a></span> <span class="preprocessor">#define __OM volatile </span><span class="comment">/*! Defines 'write only' structure member permissions */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="core__cm0_8h.html#ab6caba5853a60a17e8e04499b52bf691"> 170</a></span> <span class="preprocessor">#define __IOM volatile </span><span class="comment">/*! Defines 'read / write' structure member permissions */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00171"></a><span class="lineno"> 171</span> <span class="comment"></span> </div>
<div class="line"><a name="l00172"></a><span class="lineno"> 172</span> <span class="comment">/*@} end of group Cortex_M0 */</span></div>
<div class="line"><a name="l00173"></a><span class="lineno"> 173</span>  </div>
<div class="line"><a name="l00174"></a><span class="lineno"> 174</span>  </div>
<div class="line"><a name="l00175"></a><span class="lineno"> 175</span>  </div>
<div class="line"><a name="l00176"></a><span class="lineno"> 176</span> <span class="comment">/*******************************************************************************</span></div>
<div class="line"><a name="l00177"></a><span class="lineno"> 177</span> <span class="comment"> * Register Abstraction</span></div>
<div class="line"><a name="l00178"></a><span class="lineno"> 178</span> <span class="comment"> Core Register contain:</span></div>
<div class="line"><a name="l00179"></a><span class="lineno"> 179</span> <span class="comment"> - Core Register</span></div>
<div class="line"><a name="l00180"></a><span class="lineno"> 180</span> <span class="comment"> - Core NVIC Register</span></div>
<div class="line"><a name="l00181"></a><span class="lineno"> 181</span> <span class="comment"> - Core SCB Register</span></div>
<div class="line"><a name="l00182"></a><span class="lineno"> 182</span> <span class="comment"> - Core SysTick Register</span></div>
<div class="line"><a name="l00183"></a><span class="lineno"> 183</span> <span class="comment"> ******************************************************************************/</span><span class="comment"></span></div>
<div class="line"><a name="l00184"></a><span class="lineno"> 184</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00185"></a><span class="lineno"> 185</span> <span class="comment"> \defgroup CMSIS_core_register Defines and Type Definitions</span></div>
<div class="line"><a name="l00186"></a><span class="lineno"> 186</span> <span class="comment"> \brief Type definitions and defines for Cortex-M processor based devices.</span></div>
<div class="line"><a name="l00187"></a><span class="lineno"> 187</span> <span class="comment">*/</span></div>
<div class="line"><a name="l00188"></a><span class="lineno"> 188</span> <span class="comment"></span> </div>
<div class="line"><a name="l00189"></a><span class="lineno"> 189</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00190"></a><span class="lineno"> 190</span> <span class="comment"> \ingroup CMSIS_core_register</span></div>
<div class="line"><a name="l00191"></a><span class="lineno"> 191</span> <span class="comment"> \defgroup CMSIS_CORE Status and Control Registers</span></div>
<div class="line"><a name="l00192"></a><span class="lineno"> 192</span> <span class="comment"> \brief Core Register type definitions.</span></div>
<div class="line"><a name="l00193"></a><span class="lineno"> 193</span> <span class="comment"> @{</span></div>
<div class="line"><a name="l00194"></a><span class="lineno"> 194</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00195"></a><span class="lineno"> 195</span> <span class="comment"></span> </div>
<div class="line"><a name="l00196"></a><span class="lineno"> 196</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00197"></a><span class="lineno"> 197</span> <span class="comment"> \brief Union type to access the Application Program Status Register (APSR).</span></div>
<div class="line"><a name="l00198"></a><span class="lineno"> 198</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00199"></a><span class="lineno"> 199</span> <span class="keyword">typedef</span> <span class="keyword">union</span></div>
<div class="line"><a name="l00200"></a><span class="lineno"> 200</span> {</div>
<div class="line"><a name="l00201"></a><span class="lineno"> 201</span>  <span class="keyword">struct</span></div>
<div class="line"><a name="l00202"></a><span class="lineno"> 202</span>  {</div>
<div class="line"><a name="l00203"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#ga6cdb11c1f7682987fbb9d7482183b9d3"> 203</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#ga6cdb11c1f7682987fbb9d7482183b9d3">_reserved0</a>:28; <span class="comment">/*!< bit: 0..27 Reserved */</span></div>
<div class="line"><a name="l00204"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#gac3984a2f4012a8984a5ebb59186e84e7"> 204</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#gac3984a2f4012a8984a5ebb59186e84e7">V</a>:1; <span class="comment">/*!< bit: 28 Overflow condition code flag */</span></div>
<div class="line"><a name="l00205"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#gae4179d3b9155265392f755eeebc73933"> 205</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#gae4179d3b9155265392f755eeebc73933">C</a>:1; <span class="comment">/*!< bit: 29 Carry condition code flag */</span></div>
<div class="line"><a name="l00206"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#ga2dc48ab2298b09836df267f640eb4479"> 206</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#ga2dc48ab2298b09836df267f640eb4479">Z</a>:1; <span class="comment">/*!< bit: 30 Zero condition code flag */</span></div>
<div class="line"><a name="l00207"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#gafb7954554ee392a054d8b877f33bb37e"> 207</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#gafb7954554ee392a054d8b877f33bb37e">N</a>:1; <span class="comment">/*!< bit: 31 Negative condition code flag */</span></div>
<div class="line"><a name="l00208"></a><span class="lineno"> 208</span>  } b; <span class="comment">/*!< Structure used for bit access */</span></div>
<div class="line"><a name="l00209"></a><span class="lineno"> 209</span>  uint32_t w; <span class="comment">/*!< Type used for word access */</span></div>
<div class="line"><a name="l00210"></a><span class="lineno"> 210</span> } <a class="code" href="unionAPSR__Type.html">APSR_Type</a>;</div>
<div class="line"><a name="l00211"></a><span class="lineno"> 211</span>  </div>
<div class="line"><a name="l00212"></a><span class="lineno"> 212</span> <span class="comment">/* APSR Register Definitions */</span></div>
<div class="line"><a name="l00213"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#gac469528d210043c7bd3f12f0e6824766"> 213</a></span> <span class="preprocessor">#define APSR_N_Pos 31U </span><span class="comment">/*!< APSR: N Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00214"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#gadbc2cf55a026f661b53fadfcf822cef1"> 214</a></span> <span class="preprocessor">#define APSR_N_Msk (1UL << APSR_N_Pos) </span><span class="comment">/*!< APSR: N Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00215"></a><span class="lineno"> 215</span>  </div>
<div class="line"><a name="l00216"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#ga3661286d108b1aca308d7445685eae3a"> 216</a></span> <span class="preprocessor">#define APSR_Z_Pos 30U </span><span class="comment">/*!< APSR: Z Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00217"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#ga1deb4d1aa72bb83d1f79329406f15711"> 217</a></span> <span class="preprocessor">#define APSR_Z_Msk (1UL << APSR_Z_Pos) </span><span class="comment">/*!< APSR: Z Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00218"></a><span class="lineno"> 218</span>  </div>
<div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#ga6cf72aa6f09a168f9e5beda1a4a887b9"> 219</a></span> <span class="preprocessor">#define APSR_C_Pos 29U </span><span class="comment">/*!< APSR: C Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00220"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#ga6d47803fbad455bc10bd1ce59f2f335d"> 220</a></span> <span class="preprocessor">#define APSR_C_Msk (1UL << APSR_C_Pos) </span><span class="comment">/*!< APSR: C Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00221"></a><span class="lineno"> 221</span>  </div>
<div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#gac62830f67679ccd11658c4172c3e6ea7"> 222</a></span> <span class="preprocessor">#define APSR_V_Pos 28U </span><span class="comment">/*!< APSR: V Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00223"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#ga33305d6701356bff6890b315fe8b5489"> 223</a></span> <span class="preprocessor">#define APSR_V_Msk (1UL << APSR_V_Pos) </span><span class="comment">/*!< APSR: V Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00224"></a><span class="lineno"> 224</span>  </div>
<div class="line"><a name="l00225"></a><span class="lineno"> 225</span> <span class="comment"></span> </div>
<div class="line"><a name="l00226"></a><span class="lineno"> 226</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00227"></a><span class="lineno"> 227</span> <span class="comment"> \brief Union type to access the Interrupt Program Status Register (IPSR).</span></div>
<div class="line"><a name="l00228"></a><span class="lineno"> 228</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00229"></a><span class="lineno"> 229</span> <span class="keyword">typedef</span> <span class="keyword">union</span></div>
<div class="line"><a name="l00230"></a><span class="lineno"> 230</span> {</div>
<div class="line"><a name="l00231"></a><span class="lineno"> 231</span>  <span class="keyword">struct</span></div>
<div class="line"><a name="l00232"></a><span class="lineno"> 232</span>  {</div>
<div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#ga3d6b4f4154de5bc10e89165ecd4fffb0"> 233</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#ga3d6b4f4154de5bc10e89165ecd4fffb0">ISR</a>:9; <span class="comment">/*!< bit: 0.. 8 Exception number */</span></div>
<div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#ga2ceae024ab8b106cbbebf77343e4ca85"> 234</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#ga2ceae024ab8b106cbbebf77343e4ca85">_reserved0</a>:23; <span class="comment">/*!< bit: 9..31 Reserved */</span></div>
<div class="line"><a name="l00235"></a><span class="lineno"> 235</span>  } b; <span class="comment">/*!< Structure used for bit access */</span></div>
<div class="line"><a name="l00236"></a><span class="lineno"> 236</span>  uint32_t w; <span class="comment">/*!< Type used for word access */</span></div>
<div class="line"><a name="l00237"></a><span class="lineno"> 237</span> } <a class="code" href="unionIPSR__Type.html">IPSR_Type</a>;</div>
<div class="line"><a name="l00238"></a><span class="lineno"> 238</span>  </div>
<div class="line"><a name="l00239"></a><span class="lineno"> 239</span> <span class="comment">/* IPSR Register Definitions */</span></div>
<div class="line"><a name="l00240"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#ga0e34027584d02c43811ae908a5ca9adf"> 240</a></span> <span class="preprocessor">#define IPSR_ISR_Pos 0U </span><span class="comment">/*!< IPSR: ISR Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00241"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#gaf013a4579a64d1f21f56ea9f1b33ab56"> 241</a></span> <span class="preprocessor">#define IPSR_ISR_Msk (0x1FFUL </span><span class="comment">/*<< IPSR_ISR_Pos*/</span><span class="preprocessor">) </span><span class="comment">/*!< IPSR: ISR Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00242"></a><span class="lineno"> 242</span>  </div>
<div class="line"><a name="l00243"></a><span class="lineno"> 243</span> <span class="comment"></span> </div>
<div class="line"><a name="l00244"></a><span class="lineno"> 244</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00245"></a><span class="lineno"> 245</span> <span class="comment"> \brief Union type to access the Special-Purpose Program Status Registers (xPSR).</span></div>
<div class="line"><a name="l00246"></a><span class="lineno"> 246</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00247"></a><span class="lineno"> 247</span> <span class="keyword">typedef</span> <span class="keyword">union</span></div>
<div class="line"><a name="l00248"></a><span class="lineno"> 248</span> {</div>
<div class="line"><a name="l00249"></a><span class="lineno"> 249</span>  <span class="keyword">struct</span></div>
<div class="line"><a name="l00250"></a><span class="lineno"> 250</span>  {</div>
<div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#gadea2f5ac2d0fa8aefc818cf4c92297ea"> 251</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#gadea2f5ac2d0fa8aefc818cf4c92297ea">ISR</a>:9; <span class="comment">/*!< bit: 0.. 8 Exception number */</span></div>
<div class="line"><a name="l00252"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#gaf9a16b374620ba11fef561b8356fe757"> 252</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#gaf9a16b374620ba11fef561b8356fe757">_reserved0</a>:15; <span class="comment">/*!< bit: 9..23 Reserved */</span></div>
<div class="line"><a name="l00253"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#gad2c2dfb87d20e94ba78573ad87a5a25e"> 253</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#gad2c2dfb87d20e94ba78573ad87a5a25e">T</a>:1; <span class="comment">/*!< bit: 24 Thumb bit (read 0) */</span></div>
<div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#gaed76ebf51274b4ba27d88d31915b2414"> 254</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#gaed76ebf51274b4ba27d88d31915b2414">_reserved1</a>:3; <span class="comment">/*!< bit: 25..27 Reserved */</span></div>
<div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#ga2da99054e0730f9d0a0906b4abdcba21"> 255</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#ga2da99054e0730f9d0a0906b4abdcba21">V</a>:1; <span class="comment">/*!< bit: 28 Overflow condition code flag */</span></div>
<div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#ga3626ef1d2d2f22c35446cb9d604fe446"> 256</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#ga3626ef1d2d2f22c35446cb9d604fe446">C</a>:1; <span class="comment">/*!< bit: 29 Carry condition code flag */</span></div>
<div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#gabb326da90b485d05e1d390a3f0cf3efe"> 257</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#gabb326da90b485d05e1d390a3f0cf3efe">Z</a>:1; <span class="comment">/*!< bit: 30 Zero condition code flag */</span></div>
<div class="line"><a name="l00258"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#gae4e6d4794176088009e6f15555232327"> 258</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#gae4e6d4794176088009e6f15555232327">N</a>:1; <span class="comment">/*!< bit: 31 Negative condition code flag */</span></div>
<div class="line"><a name="l00259"></a><span class="lineno"> 259</span>  } b; <span class="comment">/*!< Structure used for bit access */</span></div>
<div class="line"><a name="l00260"></a><span class="lineno"> 260</span>  uint32_t w; <span class="comment">/*!< Type used for word access */</span></div>
<div class="line"><a name="l00261"></a><span class="lineno"> 261</span> } <a class="code" href="unionxPSR__Type.html">xPSR_Type</a>;</div>
<div class="line"><a name="l00262"></a><span class="lineno"> 262</span>  </div>
<div class="line"><a name="l00263"></a><span class="lineno"> 263</span> <span class="comment">/* xPSR Register Definitions */</span></div>
<div class="line"><a name="l00264"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#ga031eb1b8ebcdb3d602d0b9f2ec82a7ae"> 264</a></span> <span class="preprocessor">#define xPSR_N_Pos 31U </span><span class="comment">/*!< xPSR: N Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00265"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#gaf600f4ff41b62cf2f3b0a59b6d2e93d6"> 265</a></span> <span class="preprocessor">#define xPSR_N_Msk (1UL << xPSR_N_Pos) </span><span class="comment">/*!< xPSR: N Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00266"></a><span class="lineno"> 266</span>  </div>
<div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#ga5869dd608eea73c80f0567d781d2230b"> 267</a></span> <span class="preprocessor">#define xPSR_Z_Pos 30U </span><span class="comment">/*!< xPSR: Z Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#ga907599209fba99f579778e662021c4f2"> 268</a></span> <span class="preprocessor">#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) </span><span class="comment">/*!< xPSR: Z Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00269"></a><span class="lineno"> 269</span>  </div>
<div class="line"><a name="l00270"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#ga14adb79b91f6634b351a1b57394e2db6"> 270</a></span> <span class="preprocessor">#define xPSR_C_Pos 29U </span><span class="comment">/*!< xPSR: C Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00271"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#ga21e2497255d380f956ca0f48d11d0775"> 271</a></span> <span class="preprocessor">#define xPSR_C_Msk (1UL << xPSR_C_Pos) </span><span class="comment">/*!< xPSR: C Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00272"></a><span class="lineno"> 272</span>  </div>
<div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#gae0cfbb394490db402623d97e6a979e00"> 273</a></span> <span class="preprocessor">#define xPSR_V_Pos 28U </span><span class="comment">/*!< xPSR: V Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00274"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#gab07f94ed3b6ee695f5af719dc27995c2"> 274</a></span> <span class="preprocessor">#define xPSR_V_Msk (1UL << xPSR_V_Pos) </span><span class="comment">/*!< xPSR: V Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00275"></a><span class="lineno"> 275</span>  </div>
<div class="line"><a name="l00276"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#ga98d801da9a49cda944f52aeae104dd38"> 276</a></span> <span class="preprocessor">#define xPSR_T_Pos 24U </span><span class="comment">/*!< xPSR: T Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00277"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#ga30ae2111816e82d47636a8d4577eb6ee"> 277</a></span> <span class="preprocessor">#define xPSR_T_Msk (1UL << xPSR_T_Pos) </span><span class="comment">/*!< xPSR: T Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00278"></a><span class="lineno"> 278</span>  </div>
<div class="line"><a name="l00279"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#ga21bff245fb1aef9683f693d9d7bb2233"> 279</a></span> <span class="preprocessor">#define xPSR_ISR_Pos 0U </span><span class="comment">/*!< xPSR: ISR Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00280"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#gadf8eed87e0081dfe1ef1c78a0ea91afd"> 280</a></span> <span class="preprocessor">#define xPSR_ISR_Msk (0x1FFUL </span><span class="comment">/*<< xPSR_ISR_Pos*/</span><span class="preprocessor">) </span><span class="comment">/*!< xPSR: ISR Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00281"></a><span class="lineno"> 281</span>  </div>
<div class="line"><a name="l00282"></a><span class="lineno"> 282</span> <span class="comment"></span> </div>
<div class="line"><a name="l00283"></a><span class="lineno"> 283</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00284"></a><span class="lineno"> 284</span> <span class="comment"> \brief Union type to access the Control Registers (CONTROL).</span></div>
<div class="line"><a name="l00285"></a><span class="lineno"> 285</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00286"></a><span class="lineno"> 286</span> <span class="keyword">typedef</span> <span class="keyword">union</span></div>
<div class="line"><a name="l00287"></a><span class="lineno"> 287</span> {</div>
<div class="line"><a name="l00288"></a><span class="lineno"> 288</span>  <span class="keyword">struct</span></div>
<div class="line"><a name="l00289"></a><span class="lineno"> 289</span>  {</div>
<div class="line"><a name="l00290"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#gac821a6be16aed295ad736b49fb44b748"> 290</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#gac821a6be16aed295ad736b49fb44b748">_reserved0</a>:1; <span class="comment">/*!< bit: 0 Reserved */</span></div>
<div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#gab84fa89e3bf07b423f4fc14c04b7c5b4"> 291</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#gab84fa89e3bf07b423f4fc14c04b7c5b4">SPSEL</a>:1; <span class="comment">/*!< bit: 1 Stack to be used */</span></div>
<div class="line"><a name="l00292"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#gae22d63f26286b5d9daa6a52c54bc9616"> 292</a></span>  uint32_t <a class="code" href="group__CMSIS__Core__SysTickFunctions.html#gae22d63f26286b5d9daa6a52c54bc9616">_reserved1</a>:30; <span class="comment">/*!< bit: 2..31 Reserved */</span></div>
<div class="line"><a name="l00293"></a><span class="lineno"> 293</span>  } b; <span class="comment">/*!< Structure used for bit access */</span></div>
<div class="line"><a name="l00294"></a><span class="lineno"> 294</span>  uint32_t w; <span class="comment">/*!< Type used for word access */</span></div>
<div class="line"><a name="l00295"></a><span class="lineno"> 295</span> } <a class="code" href="unionCONTROL__Type.html">CONTROL_Type</a>;</div>
<div class="line"><a name="l00296"></a><span class="lineno"> 296</span>  </div>
<div class="line"><a name="l00297"></a><span class="lineno"> 297</span> <span class="comment">/* CONTROL Register Definitions */</span></div>
<div class="line"><a name="l00298"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#ga07eafc53e609895342c6a530e9d01310"> 298</a></span> <span class="preprocessor">#define CONTROL_SPSEL_Pos 1U </span><span class="comment">/*!< CONTROL: SPSEL Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00299"></a><span class="lineno"><a class="line" href="group__CMSIS__CORE.html#ga70b29840969b06909da21369b0b05b53"> 299</a></span> <span class="preprocessor">#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) </span><span class="comment">/*!< CONTROL: SPSEL Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00300"></a><span class="lineno"> 300</span> <span class="comment"></span> </div>
<div class="line"><a name="l00301"></a><span class="lineno"> 301</span> <span class="comment">/*@} end of group CMSIS_CORE */</span></div>
<div class="line"><a name="l00302"></a><span class="lineno"> 302</span>  </div>
<div class="line"><a name="l00303"></a><span class="lineno"> 303</span> <span class="comment"></span> </div>
<div class="line"><a name="l00304"></a><span class="lineno"> 304</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00305"></a><span class="lineno"> 305</span> <span class="comment"> \ingroup CMSIS_core_register</span></div>
<div class="line"><a name="l00306"></a><span class="lineno"> 306</span> <span class="comment"> \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)</span></div>
<div class="line"><a name="l00307"></a><span class="lineno"> 307</span> <span class="comment"> \brief Type definitions for the NVIC Registers</span></div>
<div class="line"><a name="l00308"></a><span class="lineno"> 308</span> <span class="comment"> @{</span></div>
<div class="line"><a name="l00309"></a><span class="lineno"> 309</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00310"></a><span class="lineno"> 310</span> <span class="comment"></span> </div>
<div class="line"><a name="l00311"></a><span class="lineno"> 311</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00312"></a><span class="lineno"> 312</span> <span class="comment"> \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).</span></div>
<div class="line"><a name="l00313"></a><span class="lineno"> 313</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00314"></a><span class="lineno"> 314</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
<div class="line"><a name="l00315"></a><span class="lineno"> 315</span> {</div>
<div class="line"><a name="l00316"></a><span class="lineno"> 316</span>  <a class="code" href="core__cm0_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t ISER[1U]; <span class="comment">/*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */</span></div>
<div class="line"><a name="l00317"></a><span class="lineno"> 317</span>  uint32_t RESERVED0[31U];</div>
<div class="line"><a name="l00318"></a><span class="lineno"> 318</span>  <a class="code" href="core__cm0_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t ICER[1U]; <span class="comment">/*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */</span></div>
<div class="line"><a name="l00319"></a><span class="lineno"> 319</span>  uint32_t RSERVED1[31U];</div>
<div class="line"><a name="l00320"></a><span class="lineno"> 320</span>  <a class="code" href="core__cm0_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t ISPR[1U]; <span class="comment">/*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */</span></div>
<div class="line"><a name="l00321"></a><span class="lineno"> 321</span>  uint32_t RESERVED2[31U];</div>
<div class="line"><a name="l00322"></a><span class="lineno"> 322</span>  <a class="code" href="core__cm0_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t ICPR[1U]; <span class="comment">/*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */</span></div>
<div class="line"><a name="l00323"></a><span class="lineno"> 323</span>  uint32_t RESERVED3[31U];</div>
<div class="line"><a name="l00324"></a><span class="lineno"> 324</span>  uint32_t RESERVED4[64U];</div>
<div class="line"><a name="l00325"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#gaa13477404d0599fc305947c419ac1b80"> 325</a></span>  <a class="code" href="core__cm0_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t IP[8U]; <span class="comment">/*!< Offset: 0x300 (R/W) Interrupt Priority Register */</span></div>
<div class="line"><a name="l00326"></a><span class="lineno"> 326</span> } <a class="code" href="structNVIC__Type.html">NVIC_Type</a>;</div>
<div class="line"><a name="l00327"></a><span class="lineno"> 327</span> <span class="comment"></span> </div>
<div class="line"><a name="l00328"></a><span class="lineno"> 328</span> <span class="comment">/*@} end of group CMSIS_NVIC */</span></div>
<div class="line"><a name="l00329"></a><span class="lineno"> 329</span>  </div>
<div class="line"><a name="l00330"></a><span class="lineno"> 330</span> <span class="comment"></span> </div>
<div class="line"><a name="l00331"></a><span class="lineno"> 331</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00332"></a><span class="lineno"> 332</span> <span class="comment"> \ingroup CMSIS_core_register</span></div>
<div class="line"><a name="l00333"></a><span class="lineno"> 333</span> <span class="comment"> \defgroup CMSIS_SCB System Control Block (SCB)</span></div>
<div class="line"><a name="l00334"></a><span class="lineno"> 334</span> <span class="comment"> \brief Type definitions for the System Control Block Registers</span></div>
<div class="line"><a name="l00335"></a><span class="lineno"> 335</span> <span class="comment"> @{</span></div>
<div class="line"><a name="l00336"></a><span class="lineno"> 336</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00337"></a><span class="lineno"> 337</span> <span class="comment"></span> </div>
<div class="line"><a name="l00338"></a><span class="lineno"> 338</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00339"></a><span class="lineno"> 339</span> <span class="comment"> \brief Structure type to access the System Control Block (SCB).</span></div>
<div class="line"><a name="l00340"></a><span class="lineno"> 340</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00341"></a><span class="lineno"> 341</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
<div class="line"><a name="l00342"></a><span class="lineno"> 342</span> {</div>
<div class="line"><a name="l00343"></a><span class="lineno"> 343</span>  <a class="code" href="core__cm0_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t CPUID; <span class="comment">/*!< Offset: 0x000 (R/ ) CPUID Base Register */</span></div>
<div class="line"><a name="l00344"></a><span class="lineno"> 344</span>  <a class="code" href="core__cm0_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t ICSR; <span class="comment">/*!< Offset: 0x004 (R/W) Interrupt Control and State Register */</span></div>
<div class="line"><a name="l00345"></a><span class="lineno"> 345</span>  uint32_t RESERVED0;</div>
<div class="line"><a name="l00346"></a><span class="lineno"> 346</span>  <a class="code" href="core__cm0_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t AIRCR; <span class="comment">/*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */</span></div>
<div class="line"><a name="l00347"></a><span class="lineno"> 347</span>  <a class="code" href="core__cm0_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t SCR; <span class="comment">/*!< Offset: 0x010 (R/W) System Control Register */</span></div>
<div class="line"><a name="l00348"></a><span class="lineno"> 348</span>  <a class="code" href="core__cm0_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t CCR; <span class="comment">/*!< Offset: 0x014 (R/W) Configuration Control Register */</span></div>
<div class="line"><a name="l00349"></a><span class="lineno"> 349</span>  uint32_t RESERVED1;</div>
<div class="line"><a name="l00350"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__SysTickFunctions.html#gac803f8566b839ea0cea46caee3ec6e27"> 350</a></span>  <a class="code" href="core__cm0_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t SHP[2U]; <span class="comment">/*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */</span></div>
<div class="line"><a name="l00351"></a><span class="lineno"> 351</span>  <a class="code" href="core__cm0_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t SHCSR; <span class="comment">/*!< Offset: 0x024 (R/W) System Handler Control and State Register */</span></div>
<div class="line"><a name="l00352"></a><span class="lineno"> 352</span> } <a class="code" href="structSCB__Type.html">SCB_Type</a>;</div>
<div class="line"><a name="l00353"></a><span class="lineno"> 353</span>  </div>
<div class="line"><a name="l00354"></a><span class="lineno"> 354</span> <span class="comment">/* SCB CPUID Register Definitions */</span></div>
<div class="line"><a name="l00355"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga58686b88f94f789d4e6f429fe1ff58cf"> 355</a></span> <span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Pos 24U </span><span class="comment">/*!< SCB CPUID: IMPLEMENTER Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00356"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga0932b31faafd47656a03ced75a31d99b"> 356</a></span> <span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) </span><span class="comment">/*!< SCB CPUID: IMPLEMENTER Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00357"></a><span class="lineno"> 357</span>  </div>
<div class="line"><a name="l00358"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga104462bd0815391b4044a70bd15d3a71"> 358</a></span> <span class="preprocessor">#define SCB_CPUID_VARIANT_Pos 20U </span><span class="comment">/*!< SCB CPUID: VARIANT Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00359"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gad358dfbd04300afc1824329d128b99e8"> 359</a></span> <span class="preprocessor">#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) </span><span class="comment">/*!< SCB CPUID: VARIANT Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00360"></a><span class="lineno"> 360</span>  </div>
<div class="line"><a name="l00361"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gaf8b3236b08fb8e840efb682645fb0e98"> 361</a></span> <span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Pos 16U </span><span class="comment">/*!< SCB CPUID: ARCHITECTURE Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00362"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gafae4a1f27a927338ae9dc51a0e146213"> 362</a></span> <span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) </span><span class="comment">/*!< SCB CPUID: ARCHITECTURE Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00363"></a><span class="lineno"> 363</span>  </div>
<div class="line"><a name="l00364"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga705f68eaa9afb042ca2407dc4e4629ac"> 364</a></span> <span class="preprocessor">#define SCB_CPUID_PARTNO_Pos 4U </span><span class="comment">/*!< SCB CPUID: PARTNO Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00365"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga98e581423ca016680c238c469aba546d"> 365</a></span> <span class="preprocessor">#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) </span><span class="comment">/*!< SCB CPUID: PARTNO Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00366"></a><span class="lineno"> 366</span>  </div>
<div class="line"><a name="l00367"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga3c3d9071e574de11fb27ba57034838b1"> 367</a></span> <span class="preprocessor">#define SCB_CPUID_REVISION_Pos 0U </span><span class="comment">/*!< SCB CPUID: REVISION Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00368"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga2ec0448b6483f77e7f5d08b4b81d85df"> 368</a></span> <span class="preprocessor">#define SCB_CPUID_REVISION_Msk (0xFUL </span><span class="comment">/*<< SCB_CPUID_REVISION_Pos*/</span><span class="preprocessor">) </span><span class="comment">/*!< SCB CPUID: REVISION Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00369"></a><span class="lineno"> 369</span>  </div>
<div class="line"><a name="l00370"></a><span class="lineno"> 370</span> <span class="comment">/* SCB Interrupt Control State Register Definitions */</span></div>
<div class="line"><a name="l00371"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga750d4b52624a46d71356db4ea769573b"> 371</a></span> <span class="preprocessor">#define SCB_ICSR_NMIPENDSET_Pos 31U </span><span class="comment">/*!< SCB ICSR: NMIPENDSET Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00372"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga340e3f79e9c3607dee9f2c048b6b22e8"> 372</a></span> <span class="preprocessor">#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) </span><span class="comment">/*!< SCB ICSR: NMIPENDSET Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00373"></a><span class="lineno"> 373</span>  </div>
<div class="line"><a name="l00374"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gab5ded23d2ab1d5ff7cc7ce746205e9fe"> 374</a></span> <span class="preprocessor">#define SCB_ICSR_PENDSVSET_Pos 28U </span><span class="comment">/*!< SCB ICSR: PENDSVSET Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00375"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga1e40d93efb402763c8c00ddcc56724ff"> 375</a></span> <span class="preprocessor">#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) </span><span class="comment">/*!< SCB ICSR: PENDSVSET Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00376"></a><span class="lineno"> 376</span>  </div>
<div class="line"><a name="l00377"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gae218d9022288f89faf57187c4d542ecd"> 377</a></span> <span class="preprocessor">#define SCB_ICSR_PENDSVCLR_Pos 27U </span><span class="comment">/*!< SCB ICSR: PENDSVCLR Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00378"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga4a901ace381d3c1c74ac82b22fae2e1e"> 378</a></span> <span class="preprocessor">#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) </span><span class="comment">/*!< SCB ICSR: PENDSVCLR Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00379"></a><span class="lineno"> 379</span>  </div>
<div class="line"><a name="l00380"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga9dbb3358c6167c9c3f85661b90fb2794"> 380</a></span> <span class="preprocessor">#define SCB_ICSR_PENDSTSET_Pos 26U </span><span class="comment">/*!< SCB ICSR: PENDSTSET Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00381"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga7325b61ea0ec323ef2d5c893b112e546"> 381</a></span> <span class="preprocessor">#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) </span><span class="comment">/*!< SCB ICSR: PENDSTSET Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00382"></a><span class="lineno"> 382</span>  </div>
<div class="line"><a name="l00383"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gadbe25e4b333ece1341beb1a740168fdc"> 383</a></span> <span class="preprocessor">#define SCB_ICSR_PENDSTCLR_Pos 25U </span><span class="comment">/*!< SCB ICSR: PENDSTCLR Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00384"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gab241827d2a793269d8cd99b9b28c2157"> 384</a></span> <span class="preprocessor">#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) </span><span class="comment">/*!< SCB ICSR: PENDSTCLR Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00385"></a><span class="lineno"> 385</span>  </div>
<div class="line"><a name="l00386"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga11cb5b1f9ce167b81f31787a77e575df"> 386</a></span> <span class="preprocessor">#define SCB_ICSR_ISRPREEMPT_Pos 23U </span><span class="comment">/*!< SCB ICSR: ISRPREEMPT Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00387"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gaa966600396290808d596fe96e92ca2b5"> 387</a></span> <span class="preprocessor">#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) </span><span class="comment">/*!< SCB ICSR: ISRPREEMPT Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00388"></a><span class="lineno"> 388</span>  </div>
<div class="line"><a name="l00389"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga10749d92b9b744094b845c2eb46d4319"> 389</a></span> <span class="preprocessor">#define SCB_ICSR_ISRPENDING_Pos 22U </span><span class="comment">/*!< SCB ICSR: ISRPENDING Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00390"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga056d74fd538e5d36d3be1f28d399c877"> 390</a></span> <span class="preprocessor">#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) </span><span class="comment">/*!< SCB ICSR: ISRPENDING Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00391"></a><span class="lineno"> 391</span>  </div>
<div class="line"><a name="l00392"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gada60c92bf88d6fd21a8f49efa4a127b8"> 392</a></span> <span class="preprocessor">#define SCB_ICSR_VECTPENDING_Pos 12U </span><span class="comment">/*!< SCB ICSR: VECTPENDING Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00393"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gacb6992e7c7ddc27a370f62878a21ef72"> 393</a></span> <span class="preprocessor">#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) </span><span class="comment">/*!< SCB ICSR: VECTPENDING Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00394"></a><span class="lineno"> 394</span>  </div>
<div class="line"><a name="l00395"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gae4f602c7c5c895d5fb687b71b0979fc3"> 395</a></span> <span class="preprocessor">#define SCB_ICSR_VECTACTIVE_Pos 0U </span><span class="comment">/*!< SCB ICSR: VECTACTIVE Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00396"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga5533791a4ecf1b9301c883047b3e8396"> 396</a></span> <span class="preprocessor">#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL </span><span class="comment">/*<< SCB_ICSR_VECTACTIVE_Pos*/</span><span class="preprocessor">) </span><span class="comment">/*!< SCB ICSR: VECTACTIVE Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00397"></a><span class="lineno"> 397</span>  </div>
<div class="line"><a name="l00398"></a><span class="lineno"> 398</span> <span class="comment">/* SCB Application Interrupt and Reset Control Register Definitions */</span></div>
<div class="line"><a name="l00399"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gaaa27c0ba600bf82c3da08c748845b640"> 399</a></span> <span class="preprocessor">#define SCB_AIRCR_VECTKEY_Pos 16U </span><span class="comment">/*!< SCB AIRCR: VECTKEY Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00400"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga90c7cf0c490e7ae55f9503a7fda1dd22"> 400</a></span> <span class="preprocessor">#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) </span><span class="comment">/*!< SCB AIRCR: VECTKEY Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00401"></a><span class="lineno"> 401</span>  </div>
<div class="line"><a name="l00402"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gaec404750ff5ca07f499a3c06b62051ef"> 402</a></span> <span class="preprocessor">#define SCB_AIRCR_VECTKEYSTAT_Pos 16U </span><span class="comment">/*!< SCB AIRCR: VECTKEYSTAT Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00403"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gabacedaefeefc73d666bbe59ece904493"> 403</a></span> <span class="preprocessor">#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) </span><span class="comment">/*!< SCB AIRCR: VECTKEYSTAT Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00404"></a><span class="lineno"> 404</span>  </div>
<div class="line"><a name="l00405"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gad31dec98fbc0d33ace63cb1f1a927923"> 405</a></span> <span class="preprocessor">#define SCB_AIRCR_ENDIANESS_Pos 15U </span><span class="comment">/*!< SCB AIRCR: ENDIANESS Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00406"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga2f571f93d3d4a6eac9a3040756d3d951"> 406</a></span> <span class="preprocessor">#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) </span><span class="comment">/*!< SCB AIRCR: ENDIANESS Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00407"></a><span class="lineno"> 407</span>  </div>
<div class="line"><a name="l00408"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gaffb2737eca1eac0fc1c282a76a40953c"> 408</a></span> <span class="preprocessor">#define SCB_AIRCR_SYSRESETREQ_Pos 2U </span><span class="comment">/*!< SCB AIRCR: SYSRESETREQ Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00409"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gaae1181119559a5bd36e62afa373fa720"> 409</a></span> <span class="preprocessor">#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) </span><span class="comment">/*!< SCB AIRCR: SYSRESETREQ Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00410"></a><span class="lineno"> 410</span>  </div>
<div class="line"><a name="l00411"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gaa30a12e892bb696e61626d71359a9029"> 411</a></span> <span class="preprocessor">#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U </span><span class="comment">/*!< SCB AIRCR: VECTCLRACTIVE Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00412"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga212c5ab1c1c82c807d30d2307aa8d218"> 412</a></span> <span class="preprocessor">#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) </span><span class="comment">/*!< SCB AIRCR: VECTCLRACTIVE Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00413"></a><span class="lineno"> 413</span>  </div>
<div class="line"><a name="l00414"></a><span class="lineno"> 414</span> <span class="comment">/* SCB System Control Register Definitions */</span></div>
<div class="line"><a name="l00415"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga3bddcec40aeaf3d3a998446100fa0e44"> 415</a></span> <span class="preprocessor">#define SCB_SCR_SEVONPEND_Pos 4U </span><span class="comment">/*!< SCB SCR: SEVONPEND Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00416"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gafb98656644a14342e467505f69a997c9"> 416</a></span> <span class="preprocessor">#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) </span><span class="comment">/*!< SCB SCR: SEVONPEND Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00417"></a><span class="lineno"> 417</span>  </div>
<div class="line"><a name="l00418"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gab304f6258ec03bd9a6e7a360515c3cfe"> 418</a></span> <span class="preprocessor">#define SCB_SCR_SLEEPDEEP_Pos 2U </span><span class="comment">/*!< SCB SCR: SLEEPDEEP Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00419"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga77c06a69c63f4b3f6ec1032e911e18e7"> 419</a></span> <span class="preprocessor">#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) </span><span class="comment">/*!< SCB SCR: SLEEPDEEP Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00420"></a><span class="lineno"> 420</span>  </div>
<div class="line"><a name="l00421"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga3680a15114d7fdc1e25043b881308fe9"> 421</a></span> <span class="preprocessor">#define SCB_SCR_SLEEPONEXIT_Pos 1U </span><span class="comment">/*!< SCB SCR: SLEEPONEXIT Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00422"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga50a243e317b9a70781b02758d45b05ee"> 422</a></span> <span class="preprocessor">#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) </span><span class="comment">/*!< SCB SCR: SLEEPONEXIT Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00423"></a><span class="lineno"> 423</span>  </div>
<div class="line"><a name="l00424"></a><span class="lineno"> 424</span> <span class="comment">/* SCB Configuration Control Register Definitions */</span></div>
<div class="line"><a name="l00425"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gac2d20a250960a432cc74da59d20e2f86"> 425</a></span> <span class="preprocessor">#define SCB_CCR_STKALIGN_Pos 9U </span><span class="comment">/*!< SCB CCR: STKALIGN Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00426"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga33cf22d3d46af158a03aad25ddea1bcb"> 426</a></span> <span class="preprocessor">#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) </span><span class="comment">/*!< SCB CCR: STKALIGN Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00427"></a><span class="lineno"> 427</span>  </div>
<div class="line"><a name="l00428"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#gac4e4928b864ea10fc24dbbc57d976229"> 428</a></span> <span class="preprocessor">#define SCB_CCR_UNALIGN_TRP_Pos 3U </span><span class="comment">/*!< SCB CCR: UNALIGN_TRP Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00429"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga68c96ad594af70c007923979085c99e0"> 429</a></span> <span class="preprocessor">#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) </span><span class="comment">/*!< SCB CCR: UNALIGN_TRP Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00430"></a><span class="lineno"> 430</span>  </div>
<div class="line"><a name="l00431"></a><span class="lineno"> 431</span> <span class="comment">/* SCB System Handler Control and State Register Definitions */</span></div>
<div class="line"><a name="l00432"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga2f93ec9b243f94cdd3e94b8f0bf43641"> 432</a></span> <span class="preprocessor">#define SCB_SHCSR_SVCALLPENDED_Pos 15U </span><span class="comment">/*!< SCB SHCSR: SVCALLPENDED Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00433"></a><span class="lineno"><a class="line" href="group__CMSIS__SCB.html#ga6095a7acfbad66f52822b1392be88652"> 433</a></span> <span class="preprocessor">#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) </span><span class="comment">/*!< SCB SHCSR: SVCALLPENDED Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00434"></a><span class="lineno"> 434</span> <span class="comment"></span> </div>
<div class="line"><a name="l00435"></a><span class="lineno"> 435</span> <span class="comment">/*@} end of group CMSIS_SCB */</span></div>
<div class="line"><a name="l00436"></a><span class="lineno"> 436</span>  </div>
<div class="line"><a name="l00437"></a><span class="lineno"> 437</span> <span class="comment"></span> </div>
<div class="line"><a name="l00438"></a><span class="lineno"> 438</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00439"></a><span class="lineno"> 439</span> <span class="comment"> \ingroup CMSIS_core_register</span></div>
<div class="line"><a name="l00440"></a><span class="lineno"> 440</span> <span class="comment"> \defgroup CMSIS_SysTick System Tick Timer (SysTick)</span></div>
<div class="line"><a name="l00441"></a><span class="lineno"> 441</span> <span class="comment"> \brief Type definitions for the System Timer Registers.</span></div>
<div class="line"><a name="l00442"></a><span class="lineno"> 442</span> <span class="comment"> @{</span></div>
<div class="line"><a name="l00443"></a><span class="lineno"> 443</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00444"></a><span class="lineno"> 444</span> <span class="comment"></span> </div>
<div class="line"><a name="l00445"></a><span class="lineno"> 445</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00446"></a><span class="lineno"> 446</span> <span class="comment"> \brief Structure type to access the System Timer (SysTick).</span></div>
<div class="line"><a name="l00447"></a><span class="lineno"> 447</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00448"></a><span class="lineno"> 448</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
<div class="line"><a name="l00449"></a><span class="lineno"> 449</span> {</div>
<div class="line"><a name="l00450"></a><span class="lineno"> 450</span>  <a class="code" href="core__cm0_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t CTRL; <span class="comment">/*!< Offset: 0x000 (R/W) SysTick Control and Status Register */</span></div>
<div class="line"><a name="l00451"></a><span class="lineno"> 451</span>  <a class="code" href="core__cm0_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t LOAD; <span class="comment">/*!< Offset: 0x004 (R/W) SysTick Reload Value Register */</span></div>
<div class="line"><a name="l00452"></a><span class="lineno"> 452</span>  <a class="code" href="core__cm0_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t VAL; <span class="comment">/*!< Offset: 0x008 (R/W) SysTick Current Value Register */</span></div>
<div class="line"><a name="l00453"></a><span class="lineno"> 453</span>  <a class="code" href="core__cm0_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t CALIB; <span class="comment">/*!< Offset: 0x00C (R/ ) SysTick Calibration Register */</span></div>
<div class="line"><a name="l00454"></a><span class="lineno"> 454</span> } <a class="code" href="structSysTick__Type.html">SysTick_Type</a>;</div>
<div class="line"><a name="l00455"></a><span class="lineno"> 455</span>  </div>
<div class="line"><a name="l00456"></a><span class="lineno"> 456</span> <span class="comment">/* SysTick Control / Status Register Definitions */</span></div>
<div class="line"><a name="l00457"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#gadbb65d4a815759649db41df216ed4d60"> 457</a></span> <span class="preprocessor">#define SysTick_CTRL_COUNTFLAG_Pos 16U </span><span class="comment">/*!< SysTick CTRL: COUNTFLAG Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00458"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#ga1bf3033ecccf200f59baefe15dbb367c"> 458</a></span> <span class="preprocessor">#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) </span><span class="comment">/*!< SysTick CTRL: COUNTFLAG Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00459"></a><span class="lineno"> 459</span>  </div>
<div class="line"><a name="l00460"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#ga24fbc69a5f0b78d67fda2300257baff1"> 460</a></span> <span class="preprocessor">#define SysTick_CTRL_CLKSOURCE_Pos 2U </span><span class="comment">/*!< SysTick CTRL: CLKSOURCE Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00461"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#gaa41d06039797423a46596bd313d57373"> 461</a></span> <span class="preprocessor">#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) </span><span class="comment">/*!< SysTick CTRL: CLKSOURCE Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00462"></a><span class="lineno"> 462</span>  </div>
<div class="line"><a name="l00463"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#ga88f45bbb89ce8df3cd2b2613c7b48214"> 463</a></span> <span class="preprocessor">#define SysTick_CTRL_TICKINT_Pos 1U </span><span class="comment">/*!< SysTick CTRL: TICKINT Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00464"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#ga95bb984266ca764024836a870238a027"> 464</a></span> <span class="preprocessor">#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) </span><span class="comment">/*!< SysTick CTRL: TICKINT Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00465"></a><span class="lineno"> 465</span>  </div>
<div class="line"><a name="l00466"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#ga0b48cc1e36d92a92e4bf632890314810"> 466</a></span> <span class="preprocessor">#define SysTick_CTRL_ENABLE_Pos 0U </span><span class="comment">/*!< SysTick CTRL: ENABLE Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00467"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#ga16c9fee0ed0235524bdeb38af328fd1f"> 467</a></span> <span class="preprocessor">#define SysTick_CTRL_ENABLE_Msk (1UL </span><span class="comment">/*<< SysTick_CTRL_ENABLE_Pos*/</span><span class="preprocessor">) </span><span class="comment">/*!< SysTick CTRL: ENABLE Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00468"></a><span class="lineno"> 468</span>  </div>
<div class="line"><a name="l00469"></a><span class="lineno"> 469</span> <span class="comment">/* SysTick Reload Register Definitions */</span></div>
<div class="line"><a name="l00470"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#gaf44d10df359dc5bf5752b0894ae3bad2"> 470</a></span> <span class="preprocessor">#define SysTick_LOAD_RELOAD_Pos 0U </span><span class="comment">/*!< SysTick LOAD: RELOAD Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00471"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#ga265912a7962f0e1abd170336e579b1b1"> 471</a></span> <span class="preprocessor">#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL </span><span class="comment">/*<< SysTick_LOAD_RELOAD_Pos*/</span><span class="preprocessor">) </span><span class="comment">/*!< SysTick LOAD: RELOAD Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00472"></a><span class="lineno"> 472</span>  </div>
<div class="line"><a name="l00473"></a><span class="lineno"> 473</span> <span class="comment">/* SysTick Current Register Definitions */</span></div>
<div class="line"><a name="l00474"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#ga3208104c3b019b5de35ae8c21d5c34dd"> 474</a></span> <span class="preprocessor">#define SysTick_VAL_CURRENT_Pos 0U </span><span class="comment">/*!< SysTick VAL: CURRENT Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00475"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#gafc77b56d568930b49a2474debc75ab45"> 475</a></span> <span class="preprocessor">#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL </span><span class="comment">/*<< SysTick_VAL_CURRENT_Pos*/</span><span class="preprocessor">) </span><span class="comment">/*!< SysTick VAL: CURRENT Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00476"></a><span class="lineno"> 476</span>  </div>
<div class="line"><a name="l00477"></a><span class="lineno"> 477</span> <span class="comment">/* SysTick Calibration Register Definitions */</span></div>
<div class="line"><a name="l00478"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#ga534dbe414e7a46a6ce4c1eca1fbff409"> 478</a></span> <span class="preprocessor">#define SysTick_CALIB_NOREF_Pos 31U </span><span class="comment">/*!< SysTick CALIB: NOREF Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00479"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#ga3af0d891fdd99bcc8d8912d37830edb6"> 479</a></span> <span class="preprocessor">#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) </span><span class="comment">/*!< SysTick CALIB: NOREF Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00480"></a><span class="lineno"> 480</span>  </div>
<div class="line"><a name="l00481"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#gadd0c9cd6641b9f6a0c618e7982954860"> 481</a></span> <span class="preprocessor">#define SysTick_CALIB_SKEW_Pos 30U </span><span class="comment">/*!< SysTick CALIB: SKEW Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00482"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#ga8a6a85a87334776f33d77fd147587431"> 482</a></span> <span class="preprocessor">#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) </span><span class="comment">/*!< SysTick CALIB: SKEW Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00483"></a><span class="lineno"> 483</span>  </div>
<div class="line"><a name="l00484"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#gacae558f6e75a0bed5d826f606d8e695e"> 484</a></span> <span class="preprocessor">#define SysTick_CALIB_TENMS_Pos 0U </span><span class="comment">/*!< SysTick CALIB: TENMS Position */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00485"></a><span class="lineno"><a class="line" href="group__CMSIS__SysTick.html#gaf1e68865c5aece2ad58971225bd3e95e"> 485</a></span> <span class="preprocessor">#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL </span><span class="comment">/*<< SysTick_CALIB_TENMS_Pos*/</span><span class="preprocessor">) </span><span class="comment">/*!< SysTick CALIB: TENMS Mask */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00486"></a><span class="lineno"> 486</span> <span class="comment"></span> </div>
<div class="line"><a name="l00487"></a><span class="lineno"> 487</span> <span class="comment">/*@} end of group CMSIS_SysTick */</span></div>
<div class="line"><a name="l00488"></a><span class="lineno"> 488</span>  </div>
<div class="line"><a name="l00489"></a><span class="lineno"> 489</span> <span class="comment"></span> </div>
<div class="line"><a name="l00490"></a><span class="lineno"> 490</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00491"></a><span class="lineno"> 491</span> <span class="comment"> \ingroup CMSIS_core_register</span></div>
<div class="line"><a name="l00492"></a><span class="lineno"> 492</span> <span class="comment"> \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)</span></div>
<div class="line"><a name="l00493"></a><span class="lineno"> 493</span> <span class="comment"> \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.</span></div>
<div class="line"><a name="l00494"></a><span class="lineno"> 494</span> <span class="comment"> Therefore they are not covered by the Cortex-M0 header file.</span></div>
<div class="line"><a name="l00495"></a><span class="lineno"> 495</span> <span class="comment"> @{</span></div>
<div class="line"><a name="l00496"></a><span class="lineno"> 496</span> <span class="comment"> */</span><span class="comment"></span></div>
<div class="line"><a name="l00497"></a><span class="lineno"> 497</span> <span class="comment">/*@} end of group CMSIS_CoreDebug */</span></div>
<div class="line"><a name="l00498"></a><span class="lineno"> 498</span>  </div>
<div class="line"><a name="l00499"></a><span class="lineno"> 499</span> <span class="comment"></span> </div>
<div class="line"><a name="l00500"></a><span class="lineno"> 500</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00501"></a><span class="lineno"> 501</span> <span class="comment"> \ingroup CMSIS_core_register</span></div>
<div class="line"><a name="l00502"></a><span class="lineno"> 502</span> <span class="comment"> \defgroup CMSIS_core_bitfield Core register bit field macros</span></div>
<div class="line"><a name="l00503"></a><span class="lineno"> 503</span> <span class="comment"> \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).</span></div>
<div class="line"><a name="l00504"></a><span class="lineno"> 504</span> <span class="comment"> @{</span></div>
<div class="line"><a name="l00505"></a><span class="lineno"> 505</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00506"></a><span class="lineno"> 506</span> <span class="comment"></span> </div>
<div class="line"><a name="l00507"></a><span class="lineno"> 507</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00508"></a><span class="lineno"> 508</span> <span class="comment"> \brief Mask and shift a bit field value for use in a register bit range.</span></div>
<div class="line"><a name="l00509"></a><span class="lineno"> 509</span> <span class="comment"> \param[in] field Name of the register bit field.</span></div>
<div class="line"><a name="l00510"></a><span class="lineno"> 510</span> <span class="comment"> \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.</span></div>
<div class="line"><a name="l00511"></a><span class="lineno"> 511</span> <span class="comment"> \return Masked and shifted value.</span></div>
<div class="line"><a name="l00512"></a><span class="lineno"> 512</span> <span class="comment">*/</span></div>
<div class="line"><a name="l00513"></a><span class="lineno"><a class="line" href="group__CMSIS__core__bitfield.html#ga286e3b913dbd236c7f48ea70c8821f4e"> 513</a></span> <span class="preprocessor">#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)</span></div>
<div class="line"><a name="l00514"></a><span class="lineno"> 514</span> <span class="comment"></span> </div>
<div class="line"><a name="l00515"></a><span class="lineno"> 515</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00516"></a><span class="lineno"> 516</span> <span class="comment"> \brief Mask and shift a register value to extract a bit filed value.</span></div>
<div class="line"><a name="l00517"></a><span class="lineno"> 517</span> <span class="comment"> \param[in] field Name of the register bit field.</span></div>
<div class="line"><a name="l00518"></a><span class="lineno"> 518</span> <span class="comment"> \param[in] value Value of register. This parameter is interpreted as an uint32_t type.</span></div>
<div class="line"><a name="l00519"></a><span class="lineno"> 519</span> <span class="comment"> \return Masked and shifted bit field value.</span></div>
<div class="line"><a name="l00520"></a><span class="lineno"> 520</span> <span class="comment">*/</span></div>
<div class="line"><a name="l00521"></a><span class="lineno"><a class="line" href="group__CMSIS__core__bitfield.html#ga139b6e261c981f014f386927ca4a8444"> 521</a></span> <span class="preprocessor">#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)</span></div>
<div class="line"><a name="l00522"></a><span class="lineno"> 522</span> <span class="comment"></span> </div>
<div class="line"><a name="l00523"></a><span class="lineno"> 523</span> <span class="comment">/*@} end of group CMSIS_core_bitfield */</span></div>
<div class="line"><a name="l00524"></a><span class="lineno"> 524</span>  </div>
<div class="line"><a name="l00525"></a><span class="lineno"> 525</span> <span class="comment"></span> </div>
<div class="line"><a name="l00526"></a><span class="lineno"> 526</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00527"></a><span class="lineno"> 527</span> <span class="comment"> \ingroup CMSIS_core_register</span></div>
<div class="line"><a name="l00528"></a><span class="lineno"> 528</span> <span class="comment"> \defgroup CMSIS_core_base Core Definitions</span></div>
<div class="line"><a name="l00529"></a><span class="lineno"> 529</span> <span class="comment"> \brief Definitions for base addresses, unions, and structures.</span></div>
<div class="line"><a name="l00530"></a><span class="lineno"> 530</span> <span class="comment"> @{</span></div>
<div class="line"><a name="l00531"></a><span class="lineno"> 531</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00532"></a><span class="lineno"> 532</span>  </div>
<div class="line"><a name="l00533"></a><span class="lineno"> 533</span> <span class="comment">/* Memory mapping of Core Hardware */</span></div>
<div class="line"><a name="l00534"></a><span class="lineno"><a class="line" href="group__CMSIS__core__base.html#ga3c14ed93192c8d9143322bbf77ebf770"> 534</a></span> <span class="preprocessor">#define SCS_BASE (0xE000E000UL) </span><span class="comment">/*!< System Control Space Base Address */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00535"></a><span class="lineno"><a class="line" href="group__CMSIS__core__base.html#ga58effaac0b93006b756d33209e814646"> 535</a></span> <span class="preprocessor">#define SysTick_BASE (SCS_BASE + 0x0010UL) </span><span class="comment">/*!< SysTick Base Address */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00536"></a><span class="lineno"><a class="line" href="group__CMSIS__core__base.html#gaa0288691785a5f868238e0468b39523d"> 536</a></span> <span class="preprocessor">#define NVIC_BASE (SCS_BASE + 0x0100UL) </span><span class="comment">/*!< NVIC Base Address */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00537"></a><span class="lineno"><a class="line" href="group__CMSIS__core__base.html#gad55a7ddb8d4b2398b0c1cfec76c0d9fd"> 537</a></span> <span class="preprocessor">#define SCB_BASE (SCS_BASE + 0x0D00UL) </span><span class="comment">/*!< System Control Block Base Address */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00538"></a><span class="lineno"> 538</span>  </div>
<div class="line"><a name="l00539"></a><span class="lineno"><a class="line" href="group__CMSIS__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01"> 539</a></span> <span class="preprocessor">#define SCB ((SCB_Type *) SCB_BASE ) </span><span class="comment">/*!< SCB configuration struct */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00540"></a><span class="lineno"><a class="line" href="group__CMSIS__core__base.html#gacd96c53beeaff8f603fcda425eb295de"> 540</a></span> <span class="preprocessor">#define SysTick ((SysTick_Type *) SysTick_BASE ) </span><span class="comment">/*!< SysTick configuration struct */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00541"></a><span class="lineno"><a class="line" href="group__CMSIS__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17"> 541</a></span> <span class="preprocessor">#define NVIC ((NVIC_Type *) NVIC_BASE ) </span><span class="comment">/*!< NVIC configuration struct */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00542"></a><span class="lineno"> 542</span>  </div>
<div class="line"><a name="l00543"></a><span class="lineno"> 543</span> <span class="comment"></span> </div>
<div class="line"><a name="l00544"></a><span class="lineno"> 544</span> <span class="comment">/*@} */</span></div>
<div class="line"><a name="l00545"></a><span class="lineno"> 545</span>  </div>
<div class="line"><a name="l00546"></a><span class="lineno"> 546</span>  </div>
<div class="line"><a name="l00547"></a><span class="lineno"> 547</span>  </div>
<div class="line"><a name="l00548"></a><span class="lineno"> 548</span> <span class="comment">/*******************************************************************************</span></div>
<div class="line"><a name="l00549"></a><span class="lineno"> 549</span> <span class="comment"> * Hardware Abstraction Layer</span></div>
<div class="line"><a name="l00550"></a><span class="lineno"> 550</span> <span class="comment"> Core Function Interface contains:</span></div>
<div class="line"><a name="l00551"></a><span class="lineno"> 551</span> <span class="comment"> - Core NVIC Functions</span></div>
<div class="line"><a name="l00552"></a><span class="lineno"> 552</span> <span class="comment"> - Core SysTick Functions</span></div>
<div class="line"><a name="l00553"></a><span class="lineno"> 553</span> <span class="comment"> - Core Register Access Functions</span></div>
<div class="line"><a name="l00554"></a><span class="lineno"> 554</span> <span class="comment"> ******************************************************************************/</span><span class="comment"></span></div>
<div class="line"><a name="l00555"></a><span class="lineno"> 555</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00556"></a><span class="lineno"> 556</span> <span class="comment"> \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference</span></div>
<div class="line"><a name="l00557"></a><span class="lineno"> 557</span> <span class="comment">*/</span></div>
<div class="line"><a name="l00558"></a><span class="lineno"> 558</span>  </div>
<div class="line"><a name="l00559"></a><span class="lineno"> 559</span>  </div>
<div class="line"><a name="l00560"></a><span class="lineno"> 560</span>  </div>
<div class="line"><a name="l00561"></a><span class="lineno"> 561</span> <span class="comment">/* ########################## NVIC functions #################################### */</span><span class="comment"></span></div>
<div class="line"><a name="l00562"></a><span class="lineno"> 562</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00563"></a><span class="lineno"> 563</span> <span class="comment"> \ingroup CMSIS_Core_FunctionInterface</span></div>
<div class="line"><a name="l00564"></a><span class="lineno"> 564</span> <span class="comment"> \defgroup CMSIS_Core_NVICFunctions NVIC Functions</span></div>
<div class="line"><a name="l00565"></a><span class="lineno"> 565</span> <span class="comment"> \brief Functions that manage interrupts and exceptions via the NVIC.</span></div>
<div class="line"><a name="l00566"></a><span class="lineno"> 566</span> <span class="comment"> @{</span></div>
<div class="line"><a name="l00567"></a><span class="lineno"> 567</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00568"></a><span class="lineno"> 568</span>  </div>
<div class="line"><a name="l00569"></a><span class="lineno"> 569</span> <span class="preprocessor">#ifdef CMSIS_NVIC_VIRTUAL</span></div>
<div class="line"><a name="l00570"></a><span class="lineno"> 570</span> <span class="preprocessor"> #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE</span></div>
<div class="line"><a name="l00571"></a><span class="lineno"> 571</span> <span class="preprocessor"> #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"</span></div>
<div class="line"><a name="l00572"></a><span class="lineno"> 572</span> <span class="preprocessor"> #endif</span></div>
<div class="line"><a name="l00573"></a><span class="lineno"> 573</span> <span class="preprocessor"> #include CMSIS_NVIC_VIRTUAL_HEADER_FILE</span></div>
<div class="line"><a name="l00574"></a><span class="lineno"> 574</span> <span class="preprocessor">#else</span></div>
<div class="line"><a name="l00575"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#ga0e798d5aec68cdd8263db86a76df788f"> 575</a></span> <span class="preprocessor"> #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping</span></div>
<div class="line"><a name="l00576"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#ga4eeb9214f2264fc23c34ad5de2d3fa11"> 576</a></span> <span class="preprocessor"> #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping</span></div>
<div class="line"><a name="l00577"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#ga57b3064413dbc7459d9646020fdd8bef"> 577</a></span> <span class="preprocessor"> #define NVIC_EnableIRQ __NVIC_EnableIRQ</span></div>
<div class="line"><a name="l00578"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#ga857de13232ec65dd15087eaa15bc4a69"> 578</a></span> <span class="preprocessor"> #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ</span></div>
<div class="line"><a name="l00579"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#ga73b4e251f59cab4e9a5e234aac02ae57"> 579</a></span> <span class="preprocessor"> #define NVIC_DisableIRQ __NVIC_DisableIRQ</span></div>
<div class="line"><a name="l00580"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#gac608957a239466e9e0cbc30aa64feb3b"> 580</a></span> <span class="preprocessor"> #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ</span></div>
<div class="line"><a name="l00581"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#ga2b47e2e52cf5c48a5c3348636434b3ac"> 581</a></span> <span class="preprocessor"> #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ</span></div>
<div class="line"><a name="l00582"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#ga590cf113000a079b1f0ea3dcd5b5316c"> 582</a></span> <span class="preprocessor"> #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ</span></div>
<div class="line"><a name="l00583"></a><span class="lineno"> 583</span> <span class="comment">/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */</span></div>
<div class="line"><a name="l00584"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#gae0e9d0e2f7b6133828c71b57d4941c35"> 584</a></span> <span class="preprocessor"> #define NVIC_SetPriority __NVIC_SetPriority</span></div>
<div class="line"><a name="l00585"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#gaf59b9d0a791d2157abb319753953eceb"> 585</a></span> <span class="preprocessor"> #define NVIC_GetPriority __NVIC_GetPriority</span></div>
<div class="line"><a name="l00586"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#ga6aa0367d3642575610476bf0366f0c48"> 586</a></span> <span class="preprocessor"> #define NVIC_SystemReset __NVIC_SystemReset</span></div>
<div class="line"><a name="l00587"></a><span class="lineno"> 587</span> <span class="preprocessor">#endif </span><span class="comment">/* CMSIS_NVIC_VIRTUAL */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00588"></a><span class="lineno"> 588</span>  </div>
<div class="line"><a name="l00589"></a><span class="lineno"> 589</span> <span class="preprocessor">#ifdef CMSIS_VECTAB_VIRTUAL</span></div>
<div class="line"><a name="l00590"></a><span class="lineno"> 590</span> <span class="preprocessor"> #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE</span></div>
<div class="line"><a name="l00591"></a><span class="lineno"> 591</span> <span class="preprocessor"> #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"</span></div>
<div class="line"><a name="l00592"></a><span class="lineno"> 592</span> <span class="preprocessor"> #endif</span></div>
<div class="line"><a name="l00593"></a><span class="lineno"> 593</span> <span class="preprocessor"> #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE</span></div>
<div class="line"><a name="l00594"></a><span class="lineno"> 594</span> <span class="preprocessor">#else</span></div>
<div class="line"><a name="l00595"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#ga804af63bb4c4c317387897431814775d"> 595</a></span> <span class="preprocessor"> #define NVIC_SetVector __NVIC_SetVector</span></div>
<div class="line"><a name="l00596"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#ga955eb1c33a3dcc62af11a8385e8c0fc8"> 596</a></span> <span class="preprocessor"> #define NVIC_GetVector __NVIC_GetVector</span></div>
<div class="line"><a name="l00597"></a><span class="lineno"> 597</span> <span class="preprocessor">#endif </span><span class="comment">/* (CMSIS_VECTAB_VIRTUAL) */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00598"></a><span class="lineno"> 598</span>  </div>
<div class="line"><a name="l00599"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#ga8045d905a5ca57437d8e6f71ffcb6df5"> 599</a></span> <span class="preprocessor">#define NVIC_USER_IRQ_OFFSET 16</span></div>
<div class="line"><a name="l00600"></a><span class="lineno"> 600</span>  </div>
<div class="line"><a name="l00601"></a><span class="lineno"> 601</span>  </div>
<div class="line"><a name="l00602"></a><span class="lineno"> 602</span> <span class="comment">/* The following EXC_RETURN values are saved the LR on exception entry */</span></div>
<div class="line"><a name="l00603"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#gaa6fa2b10f756385433e08522d9e4632f"> 603</a></span> <span class="preprocessor">#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) </span><span class="comment">/* return to Handler mode, uses MSP after return */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00604"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#gaea4703101b5e679f695e231f7ee72331"> 604</a></span> <span class="preprocessor">#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) </span><span class="comment">/* return to Thread mode, uses MSP after return */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00605"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#ga9998daf0fbdf31dbc8f81cd604b58175"> 605</a></span> <span class="preprocessor">#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) </span><span class="comment">/* return to Thread mode, uses PSP after return */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00606"></a><span class="lineno"> 606</span>  </div>
<div class="line"><a name="l00607"></a><span class="lineno"> 607</span>  </div>
<div class="line"><a name="l00608"></a><span class="lineno"> 608</span> <span class="comment">/* Interrupt Priorities are WORD accessible only under Armv6-M */</span></div>
<div class="line"><a name="l00609"></a><span class="lineno"> 609</span> <span class="comment">/* The following MACROS handle generation of the register offset and byte masks */</span></div>
<div class="line"><a name="l00610"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#ga53c75b28823441c6153269f0ecbed878"> 610</a></span> <span class="preprocessor">#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)</span></div>
<div class="line"><a name="l00611"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#gaee4f7eb5d7e770ad51489dbceabb1755"> 611</a></span> <span class="preprocessor">#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )</span></div>
<div class="line"><a name="l00612"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#ga370ec4b1751a6a889d849747df3763a9"> 612</a></span> <span class="preprocessor">#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )</span></div>
<div class="line"><a name="l00613"></a><span class="lineno"> 613</span>  </div>
<div class="line"><a name="l00614"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#ga6834dd8c9c59394f1b544b57665293a4"> 614</a></span> <span class="preprocessor">#define __NVIC_SetPriorityGrouping(X) (void)(X)</span></div>
<div class="line"><a name="l00615"></a><span class="lineno"><a class="line" href="group__CMSIS__Core__NVICFunctions.html#gab2072fe50f6d7cd208f6768919f59fae"> 615</a></span> <span class="preprocessor">#define __NVIC_GetPriorityGrouping() (0U)</span></div>
<div class="line"><a name="l00616"></a><span class="lineno"> 616</span> <span class="comment"></span> </div>
<div class="line"><a name="l00617"></a><span class="lineno"> 617</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00618"></a><span class="lineno"> 618</span> <span class="comment"> \brief Enable Interrupt</span></div>
<div class="line"><a name="l00619"></a><span class="lineno"> 619</span> <span class="comment"> \details Enables a device specific interrupt in the NVIC interrupt controller.</span></div>
<div class="line"><a name="l00620"></a><span class="lineno"> 620</span> <span class="comment"> \param [in] IRQn Device specific interrupt number.</span></div>
<div class="line"><a name="l00621"></a><span class="lineno"> 621</span> <span class="comment"> \note IRQn must not be negative.</span></div>
<div class="line"><a name="l00622"></a><span class="lineno"> 622</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00623"></a><span class="lineno"> 623</span> <a class="code" href="cmsis__armcc_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <span class="keywordtype">void</span> <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga71227e1376cde11eda03fcb62f1b33ea">__NVIC_EnableIRQ</a>(<a class="code" href="group__Peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</div>
<div class="line"><a name="l00624"></a><span class="lineno"> 624</span> {</div>
<div class="line"><a name="l00625"></a><span class="lineno"> 625</span>  <span class="keywordflow">if</span> ((int32_t)(IRQn) >= 0)</div>
<div class="line"><a name="l00626"></a><span class="lineno"> 626</span>  {</div>
<div class="line"><a name="l00627"></a><span class="lineno"> 627</span>  <a class="code" href="group__CMSIS__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));</div>
<div class="line"><a name="l00628"></a><span class="lineno"> 628</span>  }</div>
<div class="line"><a name="l00629"></a><span class="lineno"> 629</span> }</div>
<div class="line"><a name="l00630"></a><span class="lineno"> 630</span>  </div>
<div class="line"><a name="l00631"></a><span class="lineno"> 631</span> <span class="comment"></span> </div>
<div class="line"><a name="l00632"></a><span class="lineno"> 632</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00633"></a><span class="lineno"> 633</span> <span class="comment"> \brief Get Interrupt Enable status</span></div>
<div class="line"><a name="l00634"></a><span class="lineno"> 634</span> <span class="comment"> \details Returns a device specific interrupt enable status from the NVIC interrupt controller.</span></div>
<div class="line"><a name="l00635"></a><span class="lineno"> 635</span> <span class="comment"> \param [in] IRQn Device specific interrupt number.</span></div>
<div class="line"><a name="l00636"></a><span class="lineno"> 636</span> <span class="comment"> \return 0 Interrupt is not enabled.</span></div>
<div class="line"><a name="l00637"></a><span class="lineno"> 637</span> <span class="comment"> \return 1 Interrupt is enabled.</span></div>
<div class="line"><a name="l00638"></a><span class="lineno"> 638</span> <span class="comment"> \note IRQn must not be negative.</span></div>
<div class="line"><a name="l00639"></a><span class="lineno"> 639</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00640"></a><span class="lineno"> 640</span> <a class="code" href="cmsis__armcc_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t <a class="code" href="group__CMSIS__Core__NVICFunctions.html#gaaeb5e7cc0eaad4e2817272e7bf742083">__NVIC_GetEnableIRQ</a>(<a class="code" href="group__Peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</div>
<div class="line"><a name="l00641"></a><span class="lineno"> 641</span> {</div>
<div class="line"><a name="l00642"></a><span class="lineno"> 642</span>  <span class="keywordflow">if</span> ((int32_t)(IRQn) >= 0)</div>
<div class="line"><a name="l00643"></a><span class="lineno"> 643</span>  {</div>
<div class="line"><a name="l00644"></a><span class="lineno"> 644</span>  <span class="keywordflow">return</span>((uint32_t)(((<a class="code" href="group__CMSIS__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));</div>
<div class="line"><a name="l00645"></a><span class="lineno"> 645</span>  }</div>
<div class="line"><a name="l00646"></a><span class="lineno"> 646</span>  <span class="keywordflow">else</span></div>
<div class="line"><a name="l00647"></a><span class="lineno"> 647</span>  {</div>
<div class="line"><a name="l00648"></a><span class="lineno"> 648</span>  <span class="keywordflow">return</span>(0U);</div>
<div class="line"><a name="l00649"></a><span class="lineno"> 649</span>  }</div>
<div class="line"><a name="l00650"></a><span class="lineno"> 650</span> }</div>
<div class="line"><a name="l00651"></a><span class="lineno"> 651</span>  </div>
<div class="line"><a name="l00652"></a><span class="lineno"> 652</span> <span class="comment"></span> </div>
<div class="line"><a name="l00653"></a><span class="lineno"> 653</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00654"></a><span class="lineno"> 654</span> <span class="comment"> \brief Disable Interrupt</span></div>
<div class="line"><a name="l00655"></a><span class="lineno"> 655</span> <span class="comment"> \details Disables a device specific interrupt in the NVIC interrupt controller.</span></div>
<div class="line"><a name="l00656"></a><span class="lineno"> 656</span> <span class="comment"> \param [in] IRQn Device specific interrupt number.</span></div>
<div class="line"><a name="l00657"></a><span class="lineno"> 657</span> <span class="comment"> \note IRQn must not be negative.</span></div>
<div class="line"><a name="l00658"></a><span class="lineno"> 658</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00659"></a><span class="lineno"> 659</span> <a class="code" href="cmsis__armcc_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <span class="keywordtype">void</span> <a class="code" href="group__CMSIS__Core__NVICFunctions.html#gae016e4c1986312044ee768806537d52f">__NVIC_DisableIRQ</a>(<a class="code" href="group__Peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</div>
<div class="line"><a name="l00660"></a><span class="lineno"> 660</span> {</div>
<div class="line"><a name="l00661"></a><span class="lineno"> 661</span>  <span class="keywordflow">if</span> ((int32_t)(IRQn) >= 0)</div>
<div class="line"><a name="l00662"></a><span class="lineno"> 662</span>  {</div>
<div class="line"><a name="l00663"></a><span class="lineno"> 663</span>  <a class="code" href="group__CMSIS__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));</div>
<div class="line"><a name="l00664"></a><span class="lineno"> 664</span>  <a class="code" href="group__CMSIS__Core__InstructionInterface.html#ga067d257a2b34565410acefb5afef2203">__DSB</a>();</div>
<div class="line"><a name="l00665"></a><span class="lineno"> 665</span>  <a class="code" href="group__CMSIS__Core__InstructionInterface.html#gaad233022e850a009fc6f7602be1182f6">__ISB</a>();</div>
<div class="line"><a name="l00666"></a><span class="lineno"> 666</span>  }</div>
<div class="line"><a name="l00667"></a><span class="lineno"> 667</span> }</div>
<div class="line"><a name="l00668"></a><span class="lineno"> 668</span>  </div>
<div class="line"><a name="l00669"></a><span class="lineno"> 669</span> <span class="comment"></span> </div>
<div class="line"><a name="l00670"></a><span class="lineno"> 670</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00671"></a><span class="lineno"> 671</span> <span class="comment"> \brief Get Pending Interrupt</span></div>
<div class="line"><a name="l00672"></a><span class="lineno"> 672</span> <span class="comment"> \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.</span></div>
<div class="line"><a name="l00673"></a><span class="lineno"> 673</span> <span class="comment"> \param [in] IRQn Device specific interrupt number.</span></div>
<div class="line"><a name="l00674"></a><span class="lineno"> 674</span> <span class="comment"> \return 0 Interrupt status is not pending.</span></div>
<div class="line"><a name="l00675"></a><span class="lineno"> 675</span> <span class="comment"> \return 1 Interrupt status is pending.</span></div>
<div class="line"><a name="l00676"></a><span class="lineno"> 676</span> <span class="comment"> \note IRQn must not be negative.</span></div>
<div class="line"><a name="l00677"></a><span class="lineno"> 677</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00678"></a><span class="lineno"> 678</span> <a class="code" href="cmsis__armcc_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga5a92ca5fa801ad7adb92be7257ab9694">__NVIC_GetPendingIRQ</a>(<a class="code" href="group__Peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</div>
<div class="line"><a name="l00679"></a><span class="lineno"> 679</span> {</div>
<div class="line"><a name="l00680"></a><span class="lineno"> 680</span>  <span class="keywordflow">if</span> ((int32_t)(IRQn) >= 0)</div>
<div class="line"><a name="l00681"></a><span class="lineno"> 681</span>  {</div>
<div class="line"><a name="l00682"></a><span class="lineno"> 682</span>  <span class="keywordflow">return</span>((uint32_t)(((<a class="code" href="group__CMSIS__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));</div>
<div class="line"><a name="l00683"></a><span class="lineno"> 683</span>  }</div>
<div class="line"><a name="l00684"></a><span class="lineno"> 684</span>  <span class="keywordflow">else</span></div>
<div class="line"><a name="l00685"></a><span class="lineno"> 685</span>  {</div>
<div class="line"><a name="l00686"></a><span class="lineno"> 686</span>  <span class="keywordflow">return</span>(0U);</div>
<div class="line"><a name="l00687"></a><span class="lineno"> 687</span>  }</div>
<div class="line"><a name="l00688"></a><span class="lineno"> 688</span> }</div>
<div class="line"><a name="l00689"></a><span class="lineno"> 689</span>  </div>
<div class="line"><a name="l00690"></a><span class="lineno"> 690</span> <span class="comment"></span> </div>
<div class="line"><a name="l00691"></a><span class="lineno"> 691</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00692"></a><span class="lineno"> 692</span> <span class="comment"> \brief Set Pending Interrupt</span></div>
<div class="line"><a name="l00693"></a><span class="lineno"> 693</span> <span class="comment"> \details Sets the pending bit of a device specific interrupt in the NVIC pending register.</span></div>
<div class="line"><a name="l00694"></a><span class="lineno"> 694</span> <span class="comment"> \param [in] IRQn Device specific interrupt number.</span></div>
<div class="line"><a name="l00695"></a><span class="lineno"> 695</span> <span class="comment"> \note IRQn must not be negative.</span></div>
<div class="line"><a name="l00696"></a><span class="lineno"> 696</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00697"></a><span class="lineno"> 697</span> <a class="code" href="cmsis__armcc_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <span class="keywordtype">void</span> <a class="code" href="group__CMSIS__Core__NVICFunctions.html#gaabefdd4b790b9a7308929938c0c1e1ad">__NVIC_SetPendingIRQ</a>(<a class="code" href="group__Peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</div>
<div class="line"><a name="l00698"></a><span class="lineno"> 698</span> {</div>
<div class="line"><a name="l00699"></a><span class="lineno"> 699</span>  <span class="keywordflow">if</span> ((int32_t)(IRQn) >= 0)</div>
<div class="line"><a name="l00700"></a><span class="lineno"> 700</span>  {</div>
<div class="line"><a name="l00701"></a><span class="lineno"> 701</span>  <a class="code" href="group__CMSIS__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));</div>
<div class="line"><a name="l00702"></a><span class="lineno"> 702</span>  }</div>
<div class="line"><a name="l00703"></a><span class="lineno"> 703</span> }</div>
<div class="line"><a name="l00704"></a><span class="lineno"> 704</span>  </div>
<div class="line"><a name="l00705"></a><span class="lineno"> 705</span> <span class="comment"></span> </div>
<div class="line"><a name="l00706"></a><span class="lineno"> 706</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00707"></a><span class="lineno"> 707</span> <span class="comment"> \brief Clear Pending Interrupt</span></div>
<div class="line"><a name="l00708"></a><span class="lineno"> 708</span> <span class="comment"> \details Clears the pending bit of a device specific interrupt in the NVIC pending register.</span></div>
<div class="line"><a name="l00709"></a><span class="lineno"> 709</span> <span class="comment"> \param [in] IRQn Device specific interrupt number.</span></div>
<div class="line"><a name="l00710"></a><span class="lineno"> 710</span> <span class="comment"> \note IRQn must not be negative.</span></div>
<div class="line"><a name="l00711"></a><span class="lineno"> 711</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00712"></a><span class="lineno"> 712</span> <a class="code" href="cmsis__armcc_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <span class="keywordtype">void</span> <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga562a86dbdf14827d0fee8fdafb04d191">__NVIC_ClearPendingIRQ</a>(<a class="code" href="group__Peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</div>
<div class="line"><a name="l00713"></a><span class="lineno"> 713</span> {</div>
<div class="line"><a name="l00714"></a><span class="lineno"> 714</span>  <span class="keywordflow">if</span> ((int32_t)(IRQn) >= 0)</div>
<div class="line"><a name="l00715"></a><span class="lineno"> 715</span>  {</div>
<div class="line"><a name="l00716"></a><span class="lineno"> 716</span>  <a class="code" href="group__CMSIS__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));</div>
<div class="line"><a name="l00717"></a><span class="lineno"> 717</span>  }</div>
<div class="line"><a name="l00718"></a><span class="lineno"> 718</span> }</div>
<div class="line"><a name="l00719"></a><span class="lineno"> 719</span>  </div>
<div class="line"><a name="l00720"></a><span class="lineno"> 720</span> <span class="comment"></span> </div>
<div class="line"><a name="l00721"></a><span class="lineno"> 721</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00722"></a><span class="lineno"> 722</span> <span class="comment"> \brief Set Interrupt Priority</span></div>
<div class="line"><a name="l00723"></a><span class="lineno"> 723</span> <span class="comment"> \details Sets the priority of a device specific interrupt or a processor exception.</span></div>
<div class="line"><a name="l00724"></a><span class="lineno"> 724</span> <span class="comment"> The interrupt number can be positive to specify a device specific interrupt,</span></div>
<div class="line"><a name="l00725"></a><span class="lineno"> 725</span> <span class="comment"> or negative to specify a processor exception.</span></div>
<div class="line"><a name="l00726"></a><span class="lineno"> 726</span> <span class="comment"> \param [in] IRQn Interrupt number.</span></div>
<div class="line"><a name="l00727"></a><span class="lineno"> 727</span> <span class="comment"> \param [in] priority Priority to set.</span></div>
<div class="line"><a name="l00728"></a><span class="lineno"> 728</span> <span class="comment"> \note The priority cannot be set for every processor exception.</span></div>
<div class="line"><a name="l00729"></a><span class="lineno"> 729</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00730"></a><span class="lineno"> 730</span> <a class="code" href="cmsis__armcc_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <span class="keywordtype">void</span> <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga505338e23563a9c074910fb14e7d45fd">__NVIC_SetPriority</a>(<a class="code" href="group__Peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t priority)</div>
<div class="line"><a name="l00731"></a><span class="lineno"> 731</span> {</div>
<div class="line"><a name="l00732"></a><span class="lineno"> 732</span>  <span class="keywordflow">if</span> ((int32_t)(IRQn) >= 0)</div>
<div class="line"><a name="l00733"></a><span class="lineno"> 733</span>  {</div>
<div class="line"><a name="l00734"></a><span class="lineno"> 734</span>  <a class="code" href="group__CMSIS__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>->IP[<a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga370ec4b1751a6a889d849747df3763a9">_IP_IDX</a>(IRQn)] = ((uint32_t)(<a class="code" href="group__CMSIS__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>->IP[<a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga370ec4b1751a6a889d849747df3763a9">_IP_IDX</a>(IRQn)] & ~(0xFFUL << <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga53c75b28823441c6153269f0ecbed878">_BIT_SHIFT</a>(IRQn))) |</div>
<div class="line"><a name="l00735"></a><span class="lineno"> 735</span>  (((priority << (8U - <a class="code" href="group__Configuration__section__for__CMSIS.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)) & (uint32_t)0xFFUL) << <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga53c75b28823441c6153269f0ecbed878">_BIT_SHIFT</a>(IRQn)));</div>
<div class="line"><a name="l00736"></a><span class="lineno"> 736</span>  }</div>
<div class="line"><a name="l00737"></a><span class="lineno"> 737</span>  <span class="keywordflow">else</span></div>
<div class="line"><a name="l00738"></a><span class="lineno"> 738</span>  {</div>
<div class="line"><a name="l00739"></a><span class="lineno"> 739</span>  <a class="code" href="group__CMSIS__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>->SHP[<a class="code" href="group__CMSIS__Core__NVICFunctions.html#gaee4f7eb5d7e770ad51489dbceabb1755">_SHP_IDX</a>(IRQn)] = ((uint32_t)(<a class="code" href="group__CMSIS__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>->SHP[<a class="code" href="group__CMSIS__Core__NVICFunctions.html#gaee4f7eb5d7e770ad51489dbceabb1755">_SHP_IDX</a>(IRQn)] & ~(0xFFUL << <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga53c75b28823441c6153269f0ecbed878">_BIT_SHIFT</a>(IRQn))) |</div>
<div class="line"><a name="l00740"></a><span class="lineno"> 740</span>  (((priority << (8U - <a class="code" href="group__Configuration__section__for__CMSIS.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)) & (uint32_t)0xFFUL) << <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga53c75b28823441c6153269f0ecbed878">_BIT_SHIFT</a>(IRQn)));</div>
<div class="line"><a name="l00741"></a><span class="lineno"> 741</span>  }</div>
<div class="line"><a name="l00742"></a><span class="lineno"> 742</span> }</div>
<div class="line"><a name="l00743"></a><span class="lineno"> 743</span>  </div>
<div class="line"><a name="l00744"></a><span class="lineno"> 744</span> <span class="comment"></span> </div>
<div class="line"><a name="l00745"></a><span class="lineno"> 745</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00746"></a><span class="lineno"> 746</span> <span class="comment"> \brief Get Interrupt Priority</span></div>
<div class="line"><a name="l00747"></a><span class="lineno"> 747</span> <span class="comment"> \details Reads the priority of a device specific interrupt or a processor exception.</span></div>
<div class="line"><a name="l00748"></a><span class="lineno"> 748</span> <span class="comment"> The interrupt number can be positive to specify a device specific interrupt,</span></div>
<div class="line"><a name="l00749"></a><span class="lineno"> 749</span> <span class="comment"> or negative to specify a processor exception.</span></div>
<div class="line"><a name="l00750"></a><span class="lineno"> 750</span> <span class="comment"> \param [in] IRQn Interrupt number.</span></div>
<div class="line"><a name="l00751"></a><span class="lineno"> 751</span> <span class="comment"> \return Interrupt Priority.</span></div>
<div class="line"><a name="l00752"></a><span class="lineno"> 752</span> <span class="comment"> Value is aligned automatically to the implemented priority bits of the microcontroller.</span></div>
<div class="line"><a name="l00753"></a><span class="lineno"> 753</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00754"></a><span class="lineno"> 754</span> <a class="code" href="cmsis__armcc_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t <a class="code" href="group__CMSIS__Core__NVICFunctions.html#gaeb9dc99c8e7700668813144261b0bc73">__NVIC_GetPriority</a>(<a class="code" href="group__Peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</div>
<div class="line"><a name="l00755"></a><span class="lineno"> 755</span> {</div>
<div class="line"><a name="l00756"></a><span class="lineno"> 756</span>  </div>
<div class="line"><a name="l00757"></a><span class="lineno"> 757</span>  <span class="keywordflow">if</span> ((int32_t)(IRQn) >= 0)</div>
<div class="line"><a name="l00758"></a><span class="lineno"> 758</span>  {</div>
<div class="line"><a name="l00759"></a><span class="lineno"> 759</span>  <span class="keywordflow">return</span>((uint32_t)(((<a class="code" href="group__CMSIS__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>->IP[ <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga370ec4b1751a6a889d849747df3763a9">_IP_IDX</a>(IRQn)] >> <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga53c75b28823441c6153269f0ecbed878">_BIT_SHIFT</a>(IRQn) ) & (uint32_t)0xFFUL) >> (8U - <a class="code" href="group__Configuration__section__for__CMSIS.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)));</div>
<div class="line"><a name="l00760"></a><span class="lineno"> 760</span>  }</div>
<div class="line"><a name="l00761"></a><span class="lineno"> 761</span>  <span class="keywordflow">else</span></div>
<div class="line"><a name="l00762"></a><span class="lineno"> 762</span>  {</div>
<div class="line"><a name="l00763"></a><span class="lineno"> 763</span>  <span class="keywordflow">return</span>((uint32_t)(((<a class="code" href="group__CMSIS__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>->SHP[<a class="code" href="group__CMSIS__Core__NVICFunctions.html#gaee4f7eb5d7e770ad51489dbceabb1755">_SHP_IDX</a>(IRQn)] >> <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga53c75b28823441c6153269f0ecbed878">_BIT_SHIFT</a>(IRQn) ) & (uint32_t)0xFFUL) >> (8U - <a class="code" href="group__Configuration__section__for__CMSIS.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)));</div>
<div class="line"><a name="l00764"></a><span class="lineno"> 764</span>  }</div>
<div class="line"><a name="l00765"></a><span class="lineno"> 765</span> }</div>
<div class="line"><a name="l00766"></a><span class="lineno"> 766</span>  </div>
<div class="line"><a name="l00767"></a><span class="lineno"> 767</span> <span class="comment"></span> </div>
<div class="line"><a name="l00768"></a><span class="lineno"> 768</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00769"></a><span class="lineno"> 769</span> <span class="comment"> \brief Encode Priority</span></div>
<div class="line"><a name="l00770"></a><span class="lineno"> 770</span> <span class="comment"> \details Encodes the priority for an interrupt with the given priority group,</span></div>
<div class="line"><a name="l00771"></a><span class="lineno"> 771</span> <span class="comment"> preemptive priority value, and subpriority value.</span></div>
<div class="line"><a name="l00772"></a><span class="lineno"> 772</span> <span class="comment"> In case of a conflict between priority grouping and available</span></div>
<div class="line"><a name="l00773"></a><span class="lineno"> 773</span> <span class="comment"> priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.</span></div>
<div class="line"><a name="l00774"></a><span class="lineno"> 774</span> <span class="comment"> \param [in] PriorityGroup Used priority group.</span></div>
<div class="line"><a name="l00775"></a><span class="lineno"> 775</span> <span class="comment"> \param [in] PreemptPriority Preemptive priority value (starting from 0).</span></div>
<div class="line"><a name="l00776"></a><span class="lineno"> 776</span> <span class="comment"> \param [in] SubPriority Subpriority value (starting from 0).</span></div>
<div class="line"><a name="l00777"></a><span class="lineno"> 777</span> <span class="comment"> \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().</span></div>
<div class="line"><a name="l00778"></a><span class="lineno"> 778</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00779"></a><span class="lineno"> 779</span> <a class="code" href="cmsis__armcc_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t <a class="code" href="group__CMSIS__Core__NVICFunctions.html#gadb94ac5d892b376e4f3555ae0418ebac">NVIC_EncodePriority</a> (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</div>
<div class="line"><a name="l00780"></a><span class="lineno"> 780</span> {</div>
<div class="line"><a name="l00781"></a><span class="lineno"> 781</span>  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); <span class="comment">/* only values 0..7 are used */</span></div>
<div class="line"><a name="l00782"></a><span class="lineno"> 782</span>  uint32_t PreemptPriorityBits;</div>
<div class="line"><a name="l00783"></a><span class="lineno"> 783</span>  uint32_t SubPriorityBits;</div>
<div class="line"><a name="l00784"></a><span class="lineno"> 784</span>  </div>
<div class="line"><a name="l00785"></a><span class="lineno"> 785</span>  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(<a class="code" href="group__Configuration__section__for__CMSIS.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)) ? (uint32_t)(<a class="code" href="group__Configuration__section__for__CMSIS.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>) : (uint32_t)(7UL - PriorityGroupTmp);</div>
<div class="line"><a name="l00786"></a><span class="lineno"> 786</span>  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(<a class="code" href="group__Configuration__section__for__CMSIS.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(<a class="code" href="group__Configuration__section__for__CMSIS.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>));</div>
<div class="line"><a name="l00787"></a><span class="lineno"> 787</span>  </div>
<div class="line"><a name="l00788"></a><span class="lineno"> 788</span>  <span class="keywordflow">return</span> (</div>
<div class="line"><a name="l00789"></a><span class="lineno"> 789</span>  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |</div>
<div class="line"><a name="l00790"></a><span class="lineno"> 790</span>  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))</div>
<div class="line"><a name="l00791"></a><span class="lineno"> 791</span>  );</div>
<div class="line"><a name="l00792"></a><span class="lineno"> 792</span> }</div>
<div class="line"><a name="l00793"></a><span class="lineno"> 793</span>  </div>
<div class="line"><a name="l00794"></a><span class="lineno"> 794</span> <span class="comment"></span> </div>
<div class="line"><a name="l00795"></a><span class="lineno"> 795</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00796"></a><span class="lineno"> 796</span> <span class="comment"> \brief Decode Priority</span></div>
<div class="line"><a name="l00797"></a><span class="lineno"> 797</span> <span class="comment"> \details Decodes an interrupt priority value with a given priority group to</span></div>
<div class="line"><a name="l00798"></a><span class="lineno"> 798</span> <span class="comment"> preemptive priority value and subpriority value.</span></div>
<div class="line"><a name="l00799"></a><span class="lineno"> 799</span> <span class="comment"> In case of a conflict between priority grouping and available</span></div>
<div class="line"><a name="l00800"></a><span class="lineno"> 800</span> <span class="comment"> priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.</span></div>
<div class="line"><a name="l00801"></a><span class="lineno"> 801</span> <span class="comment"> \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().</span></div>
<div class="line"><a name="l00802"></a><span class="lineno"> 802</span> <span class="comment"> \param [in] PriorityGroup Used priority group.</span></div>
<div class="line"><a name="l00803"></a><span class="lineno"> 803</span> <span class="comment"> \param [out] pPreemptPriority Preemptive priority value (starting from 0).</span></div>
<div class="line"><a name="l00804"></a><span class="lineno"> 804</span> <span class="comment"> \param [out] pSubPriority Subpriority value (starting from 0).</span></div>
<div class="line"><a name="l00805"></a><span class="lineno"> 805</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00806"></a><span class="lineno"> 806</span> <a class="code" href="cmsis__armcc_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <span class="keywordtype">void</span> <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga3387607fd8a1a32cccd77d2ac672dd96">NVIC_DecodePriority</a> (uint32_t Priority, uint32_t PriorityGroup, uint32_t* <span class="keyword">const</span> pPreemptPriority, uint32_t* <span class="keyword">const</span> pSubPriority)</div>
<div class="line"><a name="l00807"></a><span class="lineno"> 807</span> {</div>
<div class="line"><a name="l00808"></a><span class="lineno"> 808</span>  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); <span class="comment">/* only values 0..7 are used */</span></div>
<div class="line"><a name="l00809"></a><span class="lineno"> 809</span>  uint32_t PreemptPriorityBits;</div>
<div class="line"><a name="l00810"></a><span class="lineno"> 810</span>  uint32_t SubPriorityBits;</div>
<div class="line"><a name="l00811"></a><span class="lineno"> 811</span>  </div>
<div class="line"><a name="l00812"></a><span class="lineno"> 812</span>  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(<a class="code" href="group__Configuration__section__for__CMSIS.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)) ? (uint32_t)(<a class="code" href="group__Configuration__section__for__CMSIS.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>) : (uint32_t)(7UL - PriorityGroupTmp);</div>
<div class="line"><a name="l00813"></a><span class="lineno"> 813</span>  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(<a class="code" href="group__Configuration__section__for__CMSIS.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(<a class="code" href="group__Configuration__section__for__CMSIS.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>));</div>
<div class="line"><a name="l00814"></a><span class="lineno"> 814</span>  </div>
<div class="line"><a name="l00815"></a><span class="lineno"> 815</span>  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);</div>
<div class="line"><a name="l00816"></a><span class="lineno"> 816</span>  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);</div>
<div class="line"><a name="l00817"></a><span class="lineno"> 817</span> }</div>
<div class="line"><a name="l00818"></a><span class="lineno"> 818</span>  </div>
<div class="line"><a name="l00819"></a><span class="lineno"> 819</span>  </div>
<div class="line"><a name="l00820"></a><span class="lineno"> 820</span> <span class="comment"></span> </div>
<div class="line"><a name="l00821"></a><span class="lineno"> 821</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00822"></a><span class="lineno"> 822</span> <span class="comment"> \brief Set Interrupt Vector</span></div>
<div class="line"><a name="l00823"></a><span class="lineno"> 823</span> <span class="comment"> \details Sets an interrupt vector in SRAM based interrupt vector table.</span></div>
<div class="line"><a name="l00824"></a><span class="lineno"> 824</span> <span class="comment"> The interrupt number can be positive to specify a device specific interrupt,</span></div>
<div class="line"><a name="l00825"></a><span class="lineno"> 825</span> <span class="comment"> or negative to specify a processor exception.</span></div>
<div class="line"><a name="l00826"></a><span class="lineno"> 826</span> <span class="comment"> Address 0 must be mapped to SRAM.</span></div>
<div class="line"><a name="l00827"></a><span class="lineno"> 827</span> <span class="comment"> \param [in] IRQn Interrupt number</span></div>
<div class="line"><a name="l00828"></a><span class="lineno"> 828</span> <span class="comment"> \param [in] vector Address of interrupt handler function</span></div>
<div class="line"><a name="l00829"></a><span class="lineno"> 829</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00830"></a><span class="lineno"> 830</span> <a class="code" href="cmsis__armcc_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <span class="keywordtype">void</span> <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga0df355460bc1783d58f9d72ee4884208">__NVIC_SetVector</a>(<a class="code" href="group__Peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t vector)</div>
<div class="line"><a name="l00831"></a><span class="lineno"> 831</span> {</div>
<div class="line"><a name="l00832"></a><span class="lineno"> 832</span>  uint32_t *vectors = (uint32_t *)0x0U;</div>
<div class="line"><a name="l00833"></a><span class="lineno"> 833</span>  vectors[(int32_t)IRQn + <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga8045d905a5ca57437d8e6f71ffcb6df5">NVIC_USER_IRQ_OFFSET</a>] = vector;</div>
<div class="line"><a name="l00834"></a><span class="lineno"> 834</span> }</div>
<div class="line"><a name="l00835"></a><span class="lineno"> 835</span>  </div>
<div class="line"><a name="l00836"></a><span class="lineno"> 836</span> <span class="comment"></span> </div>
<div class="line"><a name="l00837"></a><span class="lineno"> 837</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00838"></a><span class="lineno"> 838</span> <span class="comment"> \brief Get Interrupt Vector</span></div>
<div class="line"><a name="l00839"></a><span class="lineno"> 839</span> <span class="comment"> \details Reads an interrupt vector from interrupt vector table.</span></div>
<div class="line"><a name="l00840"></a><span class="lineno"> 840</span> <span class="comment"> The interrupt number can be positive to specify a device specific interrupt,</span></div>
<div class="line"><a name="l00841"></a><span class="lineno"> 841</span> <span class="comment"> or negative to specify a processor exception.</span></div>
<div class="line"><a name="l00842"></a><span class="lineno"> 842</span> <span class="comment"> \param [in] IRQn Interrupt number.</span></div>
<div class="line"><a name="l00843"></a><span class="lineno"> 843</span> <span class="comment"> \return Address of interrupt handler function</span></div>
<div class="line"><a name="l00844"></a><span class="lineno"> 844</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00845"></a><span class="lineno"> 845</span> <a class="code" href="cmsis__armcc_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga44b665d2afb708121d9b10c76ff00ee5">__NVIC_GetVector</a>(<a class="code" href="group__Peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</div>
<div class="line"><a name="l00846"></a><span class="lineno"> 846</span> {</div>
<div class="line"><a name="l00847"></a><span class="lineno"> 847</span>  uint32_t *vectors = (uint32_t *)0x0U;</div>
<div class="line"><a name="l00848"></a><span class="lineno"> 848</span>  <span class="keywordflow">return</span> vectors[(int32_t)IRQn + <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga8045d905a5ca57437d8e6f71ffcb6df5">NVIC_USER_IRQ_OFFSET</a>];</div>
<div class="line"><a name="l00849"></a><span class="lineno"> 849</span> }</div>
<div class="line"><a name="l00850"></a><span class="lineno"> 850</span>  </div>
<div class="line"><a name="l00851"></a><span class="lineno"> 851</span> <span class="comment"></span> </div>
<div class="line"><a name="l00852"></a><span class="lineno"> 852</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00853"></a><span class="lineno"> 853</span> <span class="comment"> \brief System Reset</span></div>
<div class="line"><a name="l00854"></a><span class="lineno"> 854</span> <span class="comment"> \details Initiates a system reset request to reset the MCU.</span></div>
<div class="line"><a name="l00855"></a><span class="lineno"> 855</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00856"></a><span class="lineno"> 856</span> <a class="code" href="cmsis__armcc_8h.html#a153a4a31b276a9758959580538720a51">__NO_RETURN</a> <a class="code" href="cmsis__armcc_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <span class="keywordtype">void</span> <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga0d9aa2d30fa54b41eb780c16e35b676c">__NVIC_SystemReset</a>(<span class="keywordtype">void</span>)</div>
<div class="line"><a name="l00857"></a><span class="lineno"> 857</span> {</div>
<div class="line"><a name="l00858"></a><span class="lineno"> 858</span>  <a class="code" href="group__CMSIS__Core__InstructionInterface.html#ga067d257a2b34565410acefb5afef2203">__DSB</a>(); <span class="comment">/* Ensure all outstanding memory accesses included</span></div>
<div class="line"><a name="l00859"></a><span class="lineno"> 859</span> <span class="comment"> buffered write are completed before reset */</span></div>
<div class="line"><a name="l00860"></a><span class="lineno"> 860</span>  <a class="code" href="group__CMSIS__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>->AIRCR = ((0x5FAUL << <a class="code" href="group__CMSIS__SCB.html#gaaa27c0ba600bf82c3da08c748845b640">SCB_AIRCR_VECTKEY_Pos</a>) |</div>
<div class="line"><a name="l00861"></a><span class="lineno"> 861</span>  <a class="code" href="group__CMSIS__SCB.html#gaae1181119559a5bd36e62afa373fa720">SCB_AIRCR_SYSRESETREQ_Msk</a>);</div>
<div class="line"><a name="l00862"></a><span class="lineno"> 862</span>  <a class="code" href="group__CMSIS__Core__InstructionInterface.html#ga067d257a2b34565410acefb5afef2203">__DSB</a>(); <span class="comment">/* Ensure completion of memory access */</span></div>
<div class="line"><a name="l00863"></a><span class="lineno"> 863</span>  </div>
<div class="line"><a name="l00864"></a><span class="lineno"> 864</span>  <span class="keywordflow">for</span>(;;) <span class="comment">/* wait until reset */</span></div>
<div class="line"><a name="l00865"></a><span class="lineno"> 865</span>  {</div>
<div class="line"><a name="l00866"></a><span class="lineno"> 866</span>  <a class="code" href="group__CMSIS__Core__InstructionInterface.html#gabd585ddc865fb9b7f2493af1eee1a572">__NOP</a>();</div>
<div class="line"><a name="l00867"></a><span class="lineno"> 867</span>  }</div>
<div class="line"><a name="l00868"></a><span class="lineno"> 868</span> }</div>
<div class="line"><a name="l00869"></a><span class="lineno"> 869</span> <span class="comment"></span> </div>
<div class="line"><a name="l00870"></a><span class="lineno"> 870</span> <span class="comment">/*@} end of CMSIS_Core_NVICFunctions */</span></div>
<div class="line"><a name="l00871"></a><span class="lineno"> 871</span>  </div>
<div class="line"><a name="l00872"></a><span class="lineno"> 872</span>  </div>
<div class="line"><a name="l00873"></a><span class="lineno"> 873</span> <span class="comment">/* ########################## FPU functions #################################### */</span><span class="comment"></span></div>
<div class="line"><a name="l00874"></a><span class="lineno"> 874</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00875"></a><span class="lineno"> 875</span> <span class="comment"> \ingroup CMSIS_Core_FunctionInterface</span></div>
<div class="line"><a name="l00876"></a><span class="lineno"> 876</span> <span class="comment"> \defgroup CMSIS_Core_FpuFunctions FPU Functions</span></div>
<div class="line"><a name="l00877"></a><span class="lineno"> 877</span> <span class="comment"> \brief Function that provides FPU type.</span></div>
<div class="line"><a name="l00878"></a><span class="lineno"> 878</span> <span class="comment"> @{</span></div>
<div class="line"><a name="l00879"></a><span class="lineno"> 879</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00880"></a><span class="lineno"> 880</span> <span class="comment"></span> </div>
<div class="line"><a name="l00881"></a><span class="lineno"> 881</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00882"></a><span class="lineno"> 882</span> <span class="comment"> \brief get FPU type</span></div>
<div class="line"><a name="l00883"></a><span class="lineno"> 883</span> <span class="comment"> \details returns the FPU type</span></div>
<div class="line"><a name="l00884"></a><span class="lineno"> 884</span> <span class="comment"> \returns</span></div>
<div class="line"><a name="l00885"></a><span class="lineno"> 885</span> <span class="comment"> - \b 0: No FPU</span></div>
<div class="line"><a name="l00886"></a><span class="lineno"> 886</span> <span class="comment"> - \b 1: Single precision FPU</span></div>
<div class="line"><a name="l00887"></a><span class="lineno"> 887</span> <span class="comment"> - \b 2: Double + Single precision FPU</span></div>
<div class="line"><a name="l00888"></a><span class="lineno"> 888</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00889"></a><span class="lineno"> 889</span> <a class="code" href="cmsis__armcc_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t <a class="code" href="group__CMSIS__Core__NVICFunctions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a>(<span class="keywordtype">void</span>)</div>
<div class="line"><a name="l00890"></a><span class="lineno"> 890</span> {</div>
<div class="line"><a name="l00891"></a><span class="lineno"> 891</span>  <span class="keywordflow">return</span> 0U; <span class="comment">/* No FPU */</span></div>
<div class="line"><a name="l00892"></a><span class="lineno"> 892</span> }</div>
<div class="line"><a name="l00893"></a><span class="lineno"> 893</span>  </div>
<div class="line"><a name="l00894"></a><span class="lineno"> 894</span> <span class="comment"></span> </div>
<div class="line"><a name="l00895"></a><span class="lineno"> 895</span> <span class="comment">/*@} end of CMSIS_Core_FpuFunctions */</span></div>
<div class="line"><a name="l00896"></a><span class="lineno"> 896</span>  </div>
<div class="line"><a name="l00897"></a><span class="lineno"> 897</span>  </div>
<div class="line"><a name="l00898"></a><span class="lineno"> 898</span>  </div>
<div class="line"><a name="l00899"></a><span class="lineno"> 899</span> <span class="comment">/* ################################## SysTick function ############################################ */</span><span class="comment"></span></div>
<div class="line"><a name="l00900"></a><span class="lineno"> 900</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00901"></a><span class="lineno"> 901</span> <span class="comment"> \ingroup CMSIS_Core_FunctionInterface</span></div>
<div class="line"><a name="l00902"></a><span class="lineno"> 902</span> <span class="comment"> \defgroup CMSIS_Core_SysTickFunctions SysTick Functions</span></div>
<div class="line"><a name="l00903"></a><span class="lineno"> 903</span> <span class="comment"> \brief Functions that configure the System.</span></div>
<div class="line"><a name="l00904"></a><span class="lineno"> 904</span> <span class="comment"> @{</span></div>
<div class="line"><a name="l00905"></a><span class="lineno"> 905</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00906"></a><span class="lineno"> 906</span>  </div>
<div class="line"><a name="l00907"></a><span class="lineno"> 907</span> <span class="preprocessor">#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)</span></div>
<div class="line"><a name="l00908"></a><span class="lineno"> 908</span> <span class="comment"></span> </div>
<div class="line"><a name="l00909"></a><span class="lineno"> 909</span> <span class="comment">/**</span></div>
<div class="line"><a name="l00910"></a><span class="lineno"> 910</span> <span class="comment"> \brief System Tick Configuration</span></div>
<div class="line"><a name="l00911"></a><span class="lineno"> 911</span> <span class="comment"> \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.</span></div>
<div class="line"><a name="l00912"></a><span class="lineno"> 912</span> <span class="comment"> Counter is in free running mode to generate periodic interrupts.</span></div>
<div class="line"><a name="l00913"></a><span class="lineno"> 913</span> <span class="comment"> \param [in] ticks Number of ticks between two interrupts.</span></div>
<div class="line"><a name="l00914"></a><span class="lineno"> 914</span> <span class="comment"> \return 0 Function succeeded.</span></div>
<div class="line"><a name="l00915"></a><span class="lineno"> 915</span> <span class="comment"> \return 1 Function failed.</span></div>
<div class="line"><a name="l00916"></a><span class="lineno"> 916</span> <span class="comment"> \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the</span></div>
<div class="line"><a name="l00917"></a><span class="lineno"> 917</span> <span class="comment"> function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b></span></div>
<div class="line"><a name="l00918"></a><span class="lineno"> 918</span> <span class="comment"> must contain a vendor-specific implementation of this function.</span></div>
<div class="line"><a name="l00919"></a><span class="lineno"> 919</span> <span class="comment"> */</span></div>
<div class="line"><a name="l00920"></a><span class="lineno"> 920</span> <a class="code" href="cmsis__armcc_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t SysTick_Config(uint32_t ticks)</div>
<div class="line"><a name="l00921"></a><span class="lineno"> 921</span> {</div>
<div class="line"><a name="l00922"></a><span class="lineno"> 922</span>  <span class="keywordflow">if</span> ((ticks - 1UL) > <a class="code" href="group__CMSIS__SysTick.html#ga265912a7962f0e1abd170336e579b1b1">SysTick_LOAD_RELOAD_Msk</a>)</div>
<div class="line"><a name="l00923"></a><span class="lineno"> 923</span>  {</div>
<div class="line"><a name="l00924"></a><span class="lineno"> 924</span>  <span class="keywordflow">return</span> (1UL); <span class="comment">/* Reload value impossible */</span></div>
<div class="line"><a name="l00925"></a><span class="lineno"> 925</span>  }</div>
<div class="line"><a name="l00926"></a><span class="lineno"> 926</span>  </div>
<div class="line"><a name="l00927"></a><span class="lineno"> 927</span>  <a class="code" href="group__CMSIS__core__base.html#gacd96c53beeaff8f603fcda425eb295de">SysTick</a>->LOAD = (uint32_t)(ticks - 1UL); <span class="comment">/* set reload register */</span></div>
<div class="line"><a name="l00928"></a><span class="lineno"> 928</span>  <a class="code" href="group__CMSIS__Core__NVICFunctions.html#gae0e9d0e2f7b6133828c71b57d4941c35">NVIC_SetPriority</a> (<a class="code" href="group__Peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a>, (1UL << <a class="code" href="group__Configuration__section__for__CMSIS.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>) - 1UL); <span class="comment">/* set Priority for Systick Interrupt */</span></div>
<div class="line"><a name="l00929"></a><span class="lineno"> 929</span>  <a class="code" href="group__CMSIS__core__base.html#gacd96c53beeaff8f603fcda425eb295de">SysTick</a>->VAL = 0UL; <span class="comment">/* Load the SysTick Counter Value */</span></div>
<div class="line"><a name="l00930"></a><span class="lineno"> 930</span>  <a class="code" href="group__CMSIS__core__base.html#gacd96c53beeaff8f603fcda425eb295de">SysTick</a>->CTRL = <a class="code" href="group__CMSIS__SysTick.html#gaa41d06039797423a46596bd313d57373">SysTick_CTRL_CLKSOURCE_Msk</a> |</div>
<div class="line"><a name="l00931"></a><span class="lineno"> 931</span>  <a class="code" href="group__CMSIS__SysTick.html#ga95bb984266ca764024836a870238a027">SysTick_CTRL_TICKINT_Msk</a> |</div>
<div class="line"><a name="l00932"></a><span class="lineno"> 932</span>  <a class="code" href="group__CMSIS__SysTick.html#ga16c9fee0ed0235524bdeb38af328fd1f">SysTick_CTRL_ENABLE_Msk</a>; <span class="comment">/* Enable SysTick IRQ and SysTick Timer */</span></div>
<div class="line"><a name="l00933"></a><span class="lineno"> 933</span>  <span class="keywordflow">return</span> (0UL); <span class="comment">/* Function successful */</span></div>
<div class="line"><a name="l00934"></a><span class="lineno"> 934</span> }</div>
<div class="line"><a name="l00935"></a><span class="lineno"> 935</span>  </div>
<div class="line"><a name="l00936"></a><span class="lineno"> 936</span> <span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00937"></a><span class="lineno"> 937</span> <span class="comment"></span> </div>
<div class="line"><a name="l00938"></a><span class="lineno"> 938</span> <span class="comment">/*@} end of CMSIS_Core_SysTickFunctions */</span></div>
<div class="line"><a name="l00939"></a><span class="lineno"> 939</span>  </div>
<div class="line"><a name="l00940"></a><span class="lineno"> 940</span>  </div>
<div class="line"><a name="l00941"></a><span class="lineno"> 941</span>  </div>
<div class="line"><a name="l00942"></a><span class="lineno"> 942</span>  </div>
<div class="line"><a name="l00943"></a><span class="lineno"> 943</span> <span class="preprocessor">#ifdef __cplusplus</span></div>
<div class="line"><a name="l00944"></a><span class="lineno"> 944</span> }</div>
<div class="line"><a name="l00945"></a><span class="lineno"> 945</span> <span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00946"></a><span class="lineno"> 946</span>  </div>
<div class="line"><a name="l00947"></a><span class="lineno"> 947</span> <span class="preprocessor">#endif </span><span class="comment">/* __CORE_CM0_H_DEPENDANT */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00948"></a><span class="lineno"> 948</span>  </div>
<div class="line"><a name="l00949"></a><span class="lineno"> 949</span> <span class="preprocessor">#endif </span><span class="comment">/* __CMSIS_GENERIC */</span><span class="preprocessor"></span></div>
</div><!-- fragment --></div><!-- contents -->
</div><!-- doc-content -->
<div class="ttc" id="agroup__CMSIS__core__base_html_gaaaf6477c2bde2f00f99e3c2fd1060b01"><div class="ttname"><a href="group__CMSIS__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a></div><div class="ttdeci">#define SCB</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00539">core_cm0.h:539</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_ga6cdb11c1f7682987fbb9d7482183b9d3"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#ga6cdb11c1f7682987fbb9d7482183b9d3">APSR_Type::@9::_reserved0</a></div><div class="ttdeci">uint32_t _reserved0</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00203">core_cm0.h:203</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_gaeb9dc99c8e7700668813144261b0bc73"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#gaeb9dc99c8e7700668813144261b0bc73">__NVIC_GetPriority</a></div><div class="ttdeci">__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)</div><div class="ttdoc">Get Interrupt Priority.</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l01471">core_armv8mbl.h:1471</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_gafb7954554ee392a054d8b877f33bb37e"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#gafb7954554ee392a054d8b877f33bb37e">APSR_Type::@9::N</a></div><div class="ttdeci">uint32_t N</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00207">core_cm0.h:207</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_ga3387607fd8a1a32cccd77d2ac672dd96"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#ga3387607fd8a1a32cccd77d2ac672dd96">NVIC_DecodePriority</a></div><div class="ttdeci">__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)</div><div class="ttdoc">Decode Priority.</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l01523">core_armv8mbl.h:1523</a></div></div>
<div class="ttc" id="agroup__CMSIS__SysTick_html_gaa41d06039797423a46596bd313d57373"><div class="ttname"><a href="group__CMSIS__SysTick.html#gaa41d06039797423a46596bd313d57373">SysTick_CTRL_CLKSOURCE_Msk</a></div><div class="ttdeci">#define SysTick_CTRL_CLKSOURCE_Msk</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00461">core_cm0.h:461</a></div></div>
<div class="ttc" id="aunionxPSR__Type_html"><div class="ttname"><a href="unionxPSR__Type.html">xPSR_Type</a></div><div class="ttdoc">Union type to access the Special-Purpose Program Status Registers (xPSR).</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l00281">core_armv8mbl.h:281</a></div></div>
<div class="ttc" id="agroup__CMSIS__SCB_html_gaae1181119559a5bd36e62afa373fa720"><div class="ttname"><a href="group__CMSIS__SCB.html#gaae1181119559a5bd36e62afa373fa720">SCB_AIRCR_SYSRESETREQ_Msk</a></div><div class="ttdeci">#define SCB_AIRCR_SYSRESETREQ_Msk</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00409">core_cm0.h:409</a></div></div>
<div class="ttc" id="acore__cm0_8h_html_ab6caba5853a60a17e8e04499b52bf691"><div class="ttname"><a href="core__cm0_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a></div><div class="ttdeci">#define __IOM</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00170">core_cm0.h:170</a></div></div>
<div class="ttc" id="aunionAPSR__Type_html"><div class="ttname"><a href="unionAPSR__Type.html">APSR_Type</a></div><div class="ttdoc">Union type to access the Application Program Status Register (APSR).</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l00233">core_armv8mbl.h:233</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_gaf9a16b374620ba11fef561b8356fe757"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#gaf9a16b374620ba11fef561b8356fe757">xPSR_Type::@11::_reserved0</a></div><div class="ttdeci">uint32_t _reserved0</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00252">core_cm0.h:252</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_gaee4f7eb5d7e770ad51489dbceabb1755"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#gaee4f7eb5d7e770ad51489dbceabb1755">_SHP_IDX</a></div><div class="ttdeci">#define _SHP_IDX(IRQn)</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00611">core_cm0.h:611</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_gad2c2dfb87d20e94ba78573ad87a5a25e"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#gad2c2dfb87d20e94ba78573ad87a5a25e">xPSR_Type::@11::T</a></div><div class="ttdeci">uint32_t T</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00253">core_cm0.h:253</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_ga53c75b28823441c6153269f0ecbed878"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#ga53c75b28823441c6153269f0ecbed878">_BIT_SHIFT</a></div><div class="ttdeci">#define _BIT_SHIFT(IRQn)</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00610">core_cm0.h:610</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_gadb94ac5d892b376e4f3555ae0418ebac"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#gadb94ac5d892b376e4f3555ae0418ebac">NVIC_EncodePriority</a></div><div class="ttdeci">__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</div><div class="ttdoc">Encode Priority.</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l01496">core_armv8mbl.h:1496</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_gae22d63f26286b5d9daa6a52c54bc9616"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#gae22d63f26286b5d9daa6a52c54bc9616">CONTROL_Type::@12::_reserved1</a></div><div class="ttdeci">uint32_t _reserved1</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00292">core_cm0.h:292</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__InstructionInterface_html_gabd585ddc865fb9b7f2493af1eee1a572"><div class="ttname"><a href="group__CMSIS__Core__InstructionInterface.html#gabd585ddc865fb9b7f2493af1eee1a572">__NOP</a></div><div class="ttdeci">#define __NOP</div><div class="ttdoc">No Operation.</div><div class="ttdef"><b>Definition:</b> <a href="cmsis__armcc_8h_source.html#l00387">cmsis_armcc.h:387</a></div></div>
<div class="ttc" id="acore__cm0_8h_html_a4cc1649793116d7c2d8afce7a4ffce43"><div class="ttname"><a href="core__cm0_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a></div><div class="ttdeci">#define __IM</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00168">core_cm0.h:168</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_gaabefdd4b790b9a7308929938c0c1e1ad"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#gaabefdd4b790b9a7308929938c0c1e1ad">__NVIC_SetPendingIRQ</a></div><div class="ttdeci">__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Set Pending Interrupt.</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l01326">core_armv8mbl.h:1326</a></div></div>
<div class="ttc" id="astructSCB__Type_html"><div class="ttname"><a href="structSCB__Type.html">SCB_Type</a></div><div class="ttdoc">Structure type to access the System Control Block (SCB).</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l00381">core_armv8mbl.h:381</a></div></div>
<div class="ttc" id="agroup__CMSIS__SysTick_html_ga95bb984266ca764024836a870238a027"><div class="ttname"><a href="group__CMSIS__SysTick.html#ga95bb984266ca764024836a870238a027">SysTick_CTRL_TICKINT_Msk</a></div><div class="ttdeci">#define SysTick_CTRL_TICKINT_Msk</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00464">core_cm0.h:464</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_gae4e6d4794176088009e6f15555232327"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#gae4e6d4794176088009e6f15555232327">xPSR_Type::@11::N</a></div><div class="ttdeci">uint32_t N</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00258">core_cm0.h:258</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__InstructionInterface_html_gaad233022e850a009fc6f7602be1182f6"><div class="ttname"><a href="group__CMSIS__Core__InstructionInterface.html#gaad233022e850a009fc6f7602be1182f6">__ISB</a></div><div class="ttdeci">#define __ISB()</div><div class="ttdoc">Instruction Synchronization Barrier.</div><div class="ttdef"><b>Definition:</b> <a href="cmsis__armcc_8h_source.html#l00418">cmsis_armcc.h:418</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_ga71227e1376cde11eda03fcb62f1b33ea"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#ga71227e1376cde11eda03fcb62f1b33ea">__NVIC_EnableIRQ</a></div><div class="ttdeci">__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Enable Interrupt.</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l01252">core_armv8mbl.h:1252</a></div></div>
<div class="ttc" id="acmsis__version_8h_html"><div class="ttname"><a href="cmsis__version_8h.html">cmsis_version.h</a></div><div class="ttdoc">CMSIS Core(M) Version definitions.</div></div>
<div class="ttc" id="agroup__Configuration__section__for__CMSIS_html_gae3fe3587d5100c787e02102ce3944460"><div class="ttname"><a href="group__Configuration__section__for__CMSIS.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a></div><div class="ttdeci">#define __NVIC_PRIO_BITS</div><div class="ttdef"><b>Definition:</b> <a href="stm32f103xb_8h_source.html#l00052">stm32f103xb.h:52</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_ga562a86dbdf14827d0fee8fdafb04d191"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#ga562a86dbdf14827d0fee8fdafb04d191">__NVIC_ClearPendingIRQ</a></div><div class="ttdeci">__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Clear Pending Interrupt.</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l01341">core_armv8mbl.h:1341</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_gadea2f5ac2d0fa8aefc818cf4c92297ea"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#gadea2f5ac2d0fa8aefc818cf4c92297ea">xPSR_Type::@11::ISR</a></div><div class="ttdeci">uint32_t ISR</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00251">core_cm0.h:251</a></div></div>
<div class="ttc" id="agroup__Peripheral__interrupt__number__definition_html_gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7"><div class="ttname"><a href="group__Peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a></div><div class="ttdeci">@ SysTick_IRQn</div><div class="ttdef"><b>Definition:</b> <a href="stm32f103xb_8h_source.html#l00080">stm32f103xb.h:80</a></div></div>
<div class="ttc" id="agroup__CMSIS__SysTick_html_ga265912a7962f0e1abd170336e579b1b1"><div class="ttname"><a href="group__CMSIS__SysTick.html#ga265912a7962f0e1abd170336e579b1b1">SysTick_LOAD_RELOAD_Msk</a></div><div class="ttdeci">#define SysTick_LOAD_RELOAD_Msk</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00471">core_cm0.h:471</a></div></div>
<div class="ttc" id="agroup__Peripheral__interrupt__number__definition_html_ga7e1129cd8a196f4284d41db3e82ad5c8"><div class="ttname"><a href="group__Peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a></div><div class="ttdeci">IRQn_Type</div><div class="ttdoc">STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_sect...</div><div class="ttdef"><b>Definition:</b> <a href="stm32f103xb_8h_source.html#l00069">stm32f103xb.h:69</a></div></div>
<div class="ttc" id="aunionCONTROL__Type_html"><div class="ttname"><a href="unionCONTROL__Type.html">CONTROL_Type</a></div><div class="ttdoc">Union type to access the Control Registers (CONTROL).</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l00320">core_armv8mbl.h:320</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_ga2ceae024ab8b106cbbebf77343e4ca85"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#ga2ceae024ab8b106cbbebf77343e4ca85">IPSR_Type::@10::_reserved0</a></div><div class="ttdeci">uint32_t _reserved0</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00234">core_cm0.h:234</a></div></div>
<div class="ttc" id="acmsis__armcc_8h_html_aba87361bfad2ae52cfe2f40c1a1dbf9c"><div class="ttname"><a href="cmsis__armcc_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a></div><div class="ttdeci">#define __STATIC_INLINE</div><div class="ttdef"><b>Definition:</b> <a href="cmsis__armcc_8h_source.html#l00059">cmsis_armcc.h:59</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_ga0df355460bc1783d58f9d72ee4884208"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#ga0df355460bc1783d58f9d72ee4884208">__NVIC_SetVector</a></div><div class="ttdeci">__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)</div><div class="ttdoc">Set Interrupt Vector.</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l01547">core_armv8mbl.h:1547</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_ga3626ef1d2d2f22c35446cb9d604fe446"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#ga3626ef1d2d2f22c35446cb9d604fe446">xPSR_Type::@11::C</a></div><div class="ttdeci">uint32_t C</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00256">core_cm0.h:256</a></div></div>
<div class="ttc" id="agroup__CMSIS__SCB_html_gaaa27c0ba600bf82c3da08c748845b640"><div class="ttname"><a href="group__CMSIS__SCB.html#gaaa27c0ba600bf82c3da08c748845b640">SCB_AIRCR_VECTKEY_Pos</a></div><div class="ttdeci">#define SCB_AIRCR_VECTKEY_Pos</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00399">core_cm0.h:399</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_ga2da99054e0730f9d0a0906b4abdcba21"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#ga2da99054e0730f9d0a0906b4abdcba21">xPSR_Type::@11::V</a></div><div class="ttdeci">uint32_t V</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00255">core_cm0.h:255</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_gae016e4c1986312044ee768806537d52f"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#gae016e4c1986312044ee768806537d52f">__NVIC_DisableIRQ</a></div><div class="ttdeci">__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Disable Interrupt.</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l01288">core_armv8mbl.h:1288</a></div></div>
<div class="ttc" id="agroup__CMSIS__core__base_html_gac8e97e8ce56ae9f57da1363a937f8a17"><div class="ttname"><a href="group__CMSIS__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a></div><div class="ttdeci">#define NVIC</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00541">core_cm0.h:541</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_ga44b665d2afb708121d9b10c76ff00ee5"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#ga44b665d2afb708121d9b10c76ff00ee5">__NVIC_GetVector</a></div><div class="ttdeci">__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)</div><div class="ttdoc">Get Interrupt Vector.</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l01566">core_armv8mbl.h:1566</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_gae4179d3b9155265392f755eeebc73933"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#gae4179d3b9155265392f755eeebc73933">APSR_Type::@9::C</a></div><div class="ttdeci">uint32_t C</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00205">core_cm0.h:205</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_gae0e9d0e2f7b6133828c71b57d4941c35"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#gae0e9d0e2f7b6133828c71b57d4941c35">NVIC_SetPriority</a></div><div class="ttdeci">#define NVIC_SetPriority</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00584">core_cm0.h:584</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_ga3d6b4f4154de5bc10e89165ecd4fffb0"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#ga3d6b4f4154de5bc10e89165ecd4fffb0">IPSR_Type::@10::ISR</a></div><div class="ttdeci">uint32_t ISR</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00233">core_cm0.h:233</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_ga370ec4b1751a6a889d849747df3763a9"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#ga370ec4b1751a6a889d849747df3763a9">_IP_IDX</a></div><div class="ttdeci">#define _IP_IDX(IRQn)</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00612">core_cm0.h:612</a></div></div>
<div class="ttc" id="acmsis__armcc_8h_html_a153a4a31b276a9758959580538720a51"><div class="ttname"><a href="cmsis__armcc_8h.html#a153a4a31b276a9758959580538720a51">__NO_RETURN</a></div><div class="ttdeci">#define __NO_RETURN</div><div class="ttdef"><b>Definition:</b> <a href="cmsis__armcc_8h_source.html#l00065">cmsis_armcc.h:65</a></div></div>
<div class="ttc" id="agroup__CMSIS__SysTick_html_ga16c9fee0ed0235524bdeb38af328fd1f"><div class="ttname"><a href="group__CMSIS__SysTick.html#ga16c9fee0ed0235524bdeb38af328fd1f">SysTick_CTRL_ENABLE_Msk</a></div><div class="ttdeci">#define SysTick_CTRL_ENABLE_Msk</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00467">core_cm0.h:467</a></div></div>
<div class="ttc" id="acmsis__compiler_8h_html"><div class="ttname"><a href="cmsis__compiler_8h.html">cmsis_compiler.h</a></div><div class="ttdoc">CMSIS compiler generic header file.</div></div>
<div class="ttc" id="astructNVIC__Type_html"><div class="ttname"><a href="structNVIC__Type.html">NVIC_Type</a></div><div class="ttdoc">Structure type to access the Nested Vectored Interrupt Controller (NVIC).</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l00351">core_armv8mbl.h:351</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_gac3984a2f4012a8984a5ebb59186e84e7"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#gac3984a2f4012a8984a5ebb59186e84e7">APSR_Type::@9::V</a></div><div class="ttdeci">uint32_t V</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00204">core_cm0.h:204</a></div></div>
<div class="ttc" id="agroup__CMSIS__core__base_html_gacd96c53beeaff8f603fcda425eb295de"><div class="ttname"><a href="group__CMSIS__core__base.html#gacd96c53beeaff8f603fcda425eb295de">SysTick</a></div><div class="ttdeci">#define SysTick</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00540">core_cm0.h:540</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_ga8045d905a5ca57437d8e6f71ffcb6df5"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#ga8045d905a5ca57437d8e6f71ffcb6df5">NVIC_USER_IRQ_OFFSET</a></div><div class="ttdeci">#define NVIC_USER_IRQ_OFFSET</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00599">core_cm0.h:599</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_gab84fa89e3bf07b423f4fc14c04b7c5b4"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#gab84fa89e3bf07b423f4fc14c04b7c5b4">CONTROL_Type::@12::SPSEL</a></div><div class="ttdeci">uint32_t SPSEL</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00291">core_cm0.h:291</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_ga2dc48ab2298b09836df267f640eb4479"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#ga2dc48ab2298b09836df267f640eb4479">APSR_Type::@9::Z</a></div><div class="ttdeci">uint32_t Z</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00206">core_cm0.h:206</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__InstructionInterface_html_ga067d257a2b34565410acefb5afef2203"><div class="ttname"><a href="group__CMSIS__Core__InstructionInterface.html#ga067d257a2b34565410acefb5afef2203">__DSB</a></div><div class="ttdeci">#define __DSB()</div><div class="ttdoc">Data Synchronization Barrier.</div><div class="ttdef"><b>Definition:</b> <a href="cmsis__armcc_8h_source.html#l00429">cmsis_armcc.h:429</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_gaed76ebf51274b4ba27d88d31915b2414"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#gaed76ebf51274b4ba27d88d31915b2414">xPSR_Type::@11::_reserved1</a></div><div class="ttdeci">uint32_t _reserved1</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00254">core_cm0.h:254</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_ga0d9aa2d30fa54b41eb780c16e35b676c"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#ga0d9aa2d30fa54b41eb780c16e35b676c">__NVIC_SystemReset</a></div><div class="ttdeci">__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)</div><div class="ttdoc">System Reset.</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l01581">core_armv8mbl.h:1581</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_ga505338e23563a9c074910fb14e7d45fd"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#ga505338e23563a9c074910fb14e7d45fd">__NVIC_SetPriority</a></div><div class="ttdeci">__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)</div><div class="ttdoc">Set Interrupt Priority.</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l01447">core_armv8mbl.h:1447</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_ga6bcad99ce80a0e7e4ddc6f2379081756"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a></div><div class="ttdeci">__STATIC_INLINE uint32_t SCB_GetFPUType(void)</div><div class="ttdoc">get FPU type</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l01791">core_armv8mbl.h:1791</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_ga5a92ca5fa801ad7adb92be7257ab9694"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#ga5a92ca5fa801ad7adb92be7257ab9694">__NVIC_GetPendingIRQ</a></div><div class="ttdeci">__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Get Pending Interrupt.</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l01307">core_armv8mbl.h:1307</a></div></div>
<div class="ttc" id="astructSysTick__Type_html"><div class="ttname"><a href="structSysTick__Type.html">SysTick_Type</a></div><div class="ttdoc">Structure type to access the System Timer (SysTick).</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l00558">core_armv8mbl.h:558</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_gabb326da90b485d05e1d390a3f0cf3efe"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#gabb326da90b485d05e1d390a3f0cf3efe">xPSR_Type::@11::Z</a></div><div class="ttdeci">uint32_t Z</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00257">core_cm0.h:257</a></div></div>
<div class="ttc" id="aunionIPSR__Type_html"><div class="ttname"><a href="unionIPSR__Type.html">IPSR_Type</a></div><div class="ttdoc">Union type to access the Interrupt Program Status Register (IPSR).</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l00263">core_armv8mbl.h:263</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__NVICFunctions_html_gaaeb5e7cc0eaad4e2817272e7bf742083"><div class="ttname"><a href="group__CMSIS__Core__NVICFunctions.html#gaaeb5e7cc0eaad4e2817272e7bf742083">__NVIC_GetEnableIRQ</a></div><div class="ttdeci">__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Get Interrupt Enable status.</div><div class="ttdef"><b>Definition:</b> <a href="core__armv8mbl_8h_source.html#l01269">core_armv8mbl.h:1269</a></div></div>
<div class="ttc" id="agroup__CMSIS__Core__SysTickFunctions_html_gac821a6be16aed295ad736b49fb44b748"><div class="ttname"><a href="group__CMSIS__Core__SysTickFunctions.html#gac821a6be16aed295ad736b49fb44b748">CONTROL_Type::@12::_reserved0</a></div><div class="ttdeci">uint32_t _reserved0</div><div class="ttdef"><b>Definition:</b> <a href="core__cm0_8h_source.html#l00290">core_cm0.h:290</a></div></div>
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