Commits included in published releases. Unpublished intermediate commits are private. Showing matches from the latest 100 commits ending at this release.
Merge pull request #21 from projf/2026-01
Will Green · Jan 28, 2026, 11:21 AM UTC
dafbe3385749
Merge pull request #20 from projf/tb-assign
Will Green · Mar 9, 2020, 3:22 PM UTC
893ab248a398
Fix assignment in test benches. Formal hasn't happened... yet.
Will Green · Mar 9, 2020, 3:20 PM UTC
edee04ed1065
Merge pull request #19 from projf/bufg
Will Green · Mar 9, 2020, 3:09 PM UTC
297a7e4e9109
Explicitly buffer clocks. Vivado was inserting a BUFG for clk_1x output but not for clk_5x. This create an issue for oserdes, which expects clocks to use the same buffers.
Will Green · Mar 9, 2020, 3:06 PM UTC
46819afa4f1b
Merge pull request #18 from projf/better-reset
Will Green · Mar 9, 2020, 2:58 PM UTC
b78082b6c81e
Consistent single reset. Include constraint files for Arty and Nexys Video.
Will Green · Mar 9, 2020, 2:55 PM UTC
7bc13a36f00d
Ensure line endings behave nicely on Windows.
Will Green · Jan 10, 2020, 11:00 AM UTC
f195d259c67d
Merge pull request #16 from projf/repo-rename
Will Green · Aug 15, 2019, 1:40 PM UTC
3c0c8edcbed0
Add note on change in repo name. Revert parameter definition location change.
Will Green · Aug 15, 2019, 1:38 PM UTC
fb458355d71a
Merge pull request #15 from projf/parameters
Will Green · Aug 10, 2019, 4:10 PM UTC
696e1c2f98d3
Switched parameter location in modules. No functional change.
Will Green · Aug 10, 2019, 4:08 PM UTC
547176582150
Add display parameter documentation: timings, coordinates, and clocks. Rename hdl directory to rtl. Fix value of o_sy in display timings example within module doc. Improve screen coordinates diagram. Minor improvements to prose.
Will Green · Jul 30, 2019, 3:46 PM UTC
eabe5160478f
Merge pull request #14 from projf/signed-demo
Will Green · Jul 11, 2019, 12:03 PM UTC
e417bcab6262
Use signed wire for screen coordinates in demos. Fix width of i_x in test_card_gradient expression.
Will Green · Jul 10, 2019, 8:57 PM UTC
54f8a528f593
Add TMDS waveform.
Will Green · Jul 2, 2019, 6:13 PM UTC
7e6a753f8452
Missed updated serializer test bench from async reset module merge.
Will Green · Jul 2, 2019, 6:00 PM UTC
d80118514c9c
Merge pull request #13 from projf/common-async-reset
Will Green · Jul 2, 2019, 5:46 PM UTC
7c3c08cd4752
Update DVI generator to use a common async reset across OSERDES2 instances. - Ensures HDMI channels have synchronised reset deassert. - Saves a few flip-flops into the bargain.
Will Green · Jul 2, 2019, 5:39 PM UTC
70a7430a695f
Add separate async reset module for OSERDES2.
Will Green · Jul 2, 2019, 5:39 PM UTC
537aae9b4f31
Minor improvement to module documentation.
Will Green · Jul 1, 2019, 5:52 PM UTC
0687ff5943b1
Utilization figures for "DVI on FPGA" were wrongly quoted for 1280x720 after the switch to signed values. 640x480 requires three *more* LUTs than 1280x720.
Will Green · Jul 1, 2019, 5:25 PM UTC
85e4030764df
Removed old diagram that is no longer used.
Will Green · Jul 1, 2019, 5:04 PM UTC
96385f0b3e07
Merge pull request #12 from projf/signed-coords
Will Green · Jul 1, 2019, 5:03 PM UTC
0b54441ceaa7
Add missing commas to documentation.
Will Green · Jul 1, 2019, 5:00 PM UTC
3c93cdd263dd
Improve explanation of new coordinates.
Will Green · Jul 1, 2019, 4:53 PM UTC
9eab7f595559
New display timings diagram. Include photograph of Pmods.
Will Green · Jul 1, 2019, 4:45 PM UTC
a40bc9ce82fb
Pixel beam position is now a signed 16-bit value. (x,y) and (h,v) have both been replaced with (sx,sy). The use of sx and sy is designed to make it easy to distinguish screen coordinates from world or model coordinates.
Will Green · Jul 1, 2019, 3:27 PM UTC
3f0dfd99f059
Fix typo in comment.
Will Green · Jul 1, 2019, 11:01 AM UTC
f6957dadb1b7
Better explanation of resolution config for demos.
Will Green · Jun 15, 2019, 7:51 PM UTC
e5faa58621d4
Coloured bars now, not border.
Will Green · Jun 15, 2019, 6:26 PM UTC
689d8ee1327a
Merge pull request #11 from projf/oserdes-async-enhancements
Will Green · Jun 15, 2019, 6:02 PM UTC
6914d703a77f
Using ASYNC_REG with serializer reset causes each TMDS encoder to get its own reset instance; FF usage increases slightly.
Will Green · Jun 15, 2019, 5:58 PM UTC
3bf22c97b6b0
Tweak grey bars so that they work better on 1-bit per colour output.
Will Green · Jun 15, 2019, 5:58 PM UTC
38b7bb00f2a4
Add ASYNC_REG attribute as recommended in UG901. Reduce number of reset register from 3 to 2. Set explicit initial values for reset and reset shift reg.
Will Green · Jun 15, 2019, 5:41 PM UTC
e20e87b15a0b
Test async clock lock and reset scenarios.
Will Green · Jun 15, 2019, 5:13 PM UTC
5fd98830b4db
Update documentation to reflect new test cards.
Will Green · Jun 15, 2019, 4:37 PM UTC
e107f8441f89
Merge pull request #10 from projf/oserdes-async-reset
Will Green · Jun 14, 2019, 2:54 PM UTC
0e310d2119ac
Improve test cards. Includes gradient test that exercises more functionality. Better utilization calculations.
Will Green · Jun 14, 2019, 2:48 PM UTC
06581d837562
Reset signal asserted out of sync with clock.
Will Green · Jun 14, 2019, 2:48 PM UTC
b23b93158612
Switched to simple Verilog async reset. I was unable to resolve the warning when using the xpm_cdc_async_rst macro. My design has the same warning, but has the advantage of being standard Verilog. Thanks to markg@prosensing.com for help with reset warnings and design.
Will Green · Jun 14, 2019, 2:47 PM UTC
422bbfc96ae9
Improve test cards. Additional utilization information.
Will Green · Jun 13, 2019, 6:07 PM UTC
d3782a87c307
Switch to xpm_cdc_async_rst macro. FPGA DVI LUT/ff usage on Vivado 2019.1 with this change is only 103/72. DVI Pmod and VGA LUT usage increases slightly on 2019.1.
Will Green · Jun 11, 2019, 11:42 AM UTC
c67e4fab49ff
Merge pull request #9 from projf/no-async-timings
Will Green · May 28, 2019, 10:30 AM UTC
ce09da42ada4
Comment formatting.
Will Green · May 28, 2019, 9:44 AM UTC
c06df70135bc
Fix comment.
Will Green · May 28, 2019, 9:39 AM UTC
3a79c8bec4a3
Trailing whitespace removal.
Will Green · May 28, 2019, 9:27 AM UTC
cd0c16164623
Remove async reset.
Will Green · May 28, 2019, 9:26 AM UTC
ec7b1c36e809
Fix links to module documentation.
Will Green · May 8, 2019, 10:21 AM UTC
3e81c3c5f03f
README perfectionist alert. :P
Will Green · May 7, 2019, 10:58 PM UTC
023846b426e0
Minor tweaks to README.
Will Green · May 7, 2019, 10:48 PM UTC
29566c874570
Merge pull request #6 from projf/signed-position
Will Green · May 7, 2019, 10:24 PM UTC
8a9b95a0f412
Minor grammar fix.
Will Green · May 7, 2019, 10:17 PM UTC
813c008923ac
Link to documentation not HDL in these cases.
Will Green · May 7, 2019, 10:16 PM UTC
673259c5a128
Fix demo link.
Will Green · May 7, 2019, 10:15 PM UTC
cc19b7eba816
Many small improvements to modules documentation.
Will Green · May 7, 2019, 10:13 PM UTC
0186fc8e843f
Further improvements to module documentation.
Will Green · May 7, 2019, 9:56 PM UTC
eaa254cd5430
Improvements to module documentation. Move architecture to modules doc.
Will Green · May 7, 2019, 9:50 PM UTC
3944ae8af7f6
Add documentation for DVI generator.
Will Green · May 7, 2019, 9:41 PM UTC
43a8ad64a124
Minor language improvement.
Will Green · May 7, 2019, 5:24 PM UTC
28f8fda0c2fb
Improve link to TMDS test bench.
Will Green · May 7, 2019, 5:21 PM UTC
ac3259ee0b22
Add links to HDL from module sections.
Will Green · May 7, 2019, 5:17 PM UTC
15759ae98713
Better module links. Add testing section.
Will Green · May 7, 2019, 5:15 PM UTC
dd5eba536a30
Minor improvements to display timings section.
Will Green · May 7, 2019, 4:45 PM UTC
5ee759bfcbcf
Add module documentation for display clocks and display timings.
Will Green · May 7, 2019, 4:39 PM UTC
287d89668ace
Clarify encoding of pixel clock.
Will Green · May 7, 2019, 3:02 PM UTC
8b62b0014199
Add Verilog test TMDS output.
Will Green · May 7, 2019, 2:37 PM UTC
78d2089690ac
Note that $display of encoded data comes from module itself.
Will Green · May 7, 2019, 2:36 PM UTC
2f63c967ace0
Remove unused 5x clock from VGA and DVI Pmod.
Will Green · May 7, 2019, 2:24 PM UTC
00c2e868900a
Improve language around 1080p60 support.
Will Green · May 7, 2019, 11:44 AM UTC
0ad4c97e66d8
Minor tweak to text.
Will Green · May 7, 2019, 11:38 AM UTC
f4d0ba71fda2
Minor tweak to titles.
Will Green · May 7, 2019, 11:36 AM UTC
5ded42eea177
Improve intro.
Will Green · May 7, 2019, 11:35 AM UTC
e5ef937db0f7
Separate out porting info.
Will Green · May 7, 2019, 11:33 AM UTC
0660b9bdacb0
Separate out module documentation.
Will Green · May 7, 2019, 11:21 AM UTC
515937dc9ffe
Fix bold for demo modules.
Will Green · May 7, 2019, 9:45 AM UTC
632612510498
Add mention of VGA Pmod.
Will Green · May 7, 2019, 9:42 AM UTC
7d38b78a0605
Add note on 1080p60 being out of spec, but still working.
Will Green · May 7, 2019, 9:35 AM UTC
39aeddfe7d1f
It's a border.
Will Green · May 6, 2019, 6:55 PM UTC
ff762db2d58e
Logically and.
Will Green · May 6, 2019, 6:48 PM UTC
7c4f66c051af
Minor improvements to text.
Will Green · May 6, 2019, 6:19 PM UTC
dad648733dcb
Display controller output includes raw beam position. - o_x and o_y are now the screen pixel positions. - o_h and o_v are the beam position, including blanking. Extended horizontal and vertical positions to 16 bits. Display controller uses logical && where appropriate. Added simple test card for resource utilization tests. Updated resource utilization to reflect new test card. Removed display enable from data channels in TMDS DVI demo (not required).
Will Green · May 6, 2019, 6:03 PM UTC
0f6853f3096c
Merge pull request #5 from projf/resource-usage
Will Green · Apr 25, 2019, 10:08 AM UTC
bb78101f2a2e
Minor improvement to language.
Will Green · Apr 24, 2019, 8:27 PM UTC
8ffc445f6538
LUT utilization reduction and report in README. Factor out common balance calculation in TMDS encoding (saves 23 LUT). Add resource utilization table to README.
Will Green · Apr 24, 2019, 8:08 PM UTC
a49779dcaa9c
Merge pull request #4 from projf/doc-fixes
Will Green · Apr 24, 2019, 6:04 PM UTC
efa313cf4bec
Minor documentation improvements.
Will Green · Apr 24, 2019, 5:58 PM UTC
10d56efb7f85
Merge pull request #3 from projf/doc-improvements
Will Green · Apr 24, 2019, 5:45 PM UTC
b7089a8a343b
Fix links to multi-word headings.
Will Green · Apr 24, 2019, 5:43 PM UTC
14d7043f7612
Documentation improvements: * Clarify different DVI encoding approaches * Expand model explanation * Add table of contents * Assorted grammar improvements
Will Green · Apr 24, 2019, 5:38 PM UTC
c656f1cfb7a8
Merge pull request #2 from projf/model-msb-display
Will Green · Apr 6, 2019, 3:06 PM UTC
58ce22075677
Output data MSB first to match Verilog and typical usage. Output data in compact format to match Verilog. Resolve Python style issues (PEP 8).
Will Green · Apr 6, 2019, 3:00 PM UTC
bc02b884ec94
Merge pull request #1 from projf/devel
Will Green · Mar 6, 2019, 9:49 PM UTC
c328900238a6
Add serializer 10:1 test bench for TMDS.
Will Green · Mar 6, 2019, 9:48 PM UTC
8664c63cbac8
Add display timings testbench, which includes 480p and 720p by default.
Will Green · Mar 6, 2019, 9:40 PM UTC
9cd0e9050ae2
Improve the TMDS model and include example output.
Will Green · Mar 6, 2019, 4:50 PM UTC
e6aa3a80ea86
Fix links to source code.
Will Green · Mar 3, 2019, 3:52 PM UTC
27ccb1b15fd7
Added reference to Python model.
Will Green · Mar 3, 2019, 3:49 PM UTC
71845b6d2670
Initial import of DVI TMDS test bench.
Will Green · Mar 3, 2019, 3:04 PM UTC
386676e2081c
Python model and Verilog design in agreement on balancing.