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| Name | Storage | Size |
|---|---|---|
| .. / Parent directory | ||
| Analog.SchDoc | Git | 71.5 KB |
| ClockAndBuffers.SchDoc | Git | 233.5 KB |
| DAC0.SchDoc | Git | 671.5 KB |
| DAC1.SchDoc | Git | 671.5 KB |
| Git |
| 39.3 KB |
| DDS Function Generator.PrjPcbStructure | Git | 47 B |
| FPGA_1.2v.SchDoc | Git | 309.0 KB |
| FPGA_3.3V.SchDoc | Git | 378.5 KB |
| FPGA_JTAG.SchDoc | Git | 167.5 KB |
| FPGA_SignalGenerator_20MHz.OutJob | Git | 18.0 KB |
| FrontPannel.SchDoc | Git | 287.5 KB |
| PCB_Gerber.zip | Git | 243.3 KB |
| PCB.CSPCBDoc | Git | 9138.5 KB |
| Power.SchDoc | Git | 432.5 KB |
bddbe4e5c| Name | Storage | Size |
|---|---|---|
| .. / Parent directory | ||
| Analog.SchDoc | Git | 71.5 KB |
| ClockAndBuffers.SchDoc | Git | 233.5 KB |
| DAC0.SchDoc | Git | 671.5 KB |
| DAC1.SchDoc | Git | 671.5 KB |
| DDS Function Generator.PrjPcb | Git | 39.3 KB |
| DDS Function Generator.PrjPcbStructure | Git | 47 B |
| FPGA_1.2v.SchDoc | Git | 309.0 KB |
| FPGA_3.3V.SchDoc | Git | 378.5 KB |
| FPGA_JTAG.SchDoc | Git | 167.5 KB |
| FPGA_SignalGenerator_20MHz.OutJob | Git | 18.0 KB |
| FrontPannel.SchDoc | Git | 287.5 KB |
| PCB_Gerber.zip | Git | 243.3 KB |
| PCB.CSPCBDoc | Git | 9138.5 KB |
| Power.SchDoc | Git | 432.5 KB |