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cv32e40p

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Design files

Name	Storage	Size
.. / Parent directory
include	Directory	—
register_file_test_wrap.sv	Git	5.9 KB
riscv_alu_basic.sv	Git	11.3 KB
riscv_alu_div.sv

bluewRe-enable trace port assertions9562cc8cf

Name	Storage	Size
.. / Parent directory
include	Directory	—
register_file_test_wrap.sv	Git	5.9 KB
riscv_alu_basic.sv	Git	11.3 KB
riscv_alu_div.sv	Git	7.1 KB
riscv_alu.sv	Git	40.2 KB
riscv_apu_disp.sv	Git	9.7 KB
riscv_compressed_decoder.sv	Git	12.3 KB
riscv_controller.sv	Git	37.7 KB
riscv_core.sv	Git	49.6 KB
riscv_cs_registers.sv	Git	40.3 KB
riscv_decoder.sv	Git	96.5 KB
riscv_ex_stage.sv	Git	20.9 KB
riscv_fetch_fifo.sv	Git	9.5 KB
riscv_hwloop_controller.sv	Git	3.5 KB
riscv_hwloop_regs.sv	Git	5.0 KB
riscv_id_stage.sv	Git	61.5 KB
riscv_if_stage.sv	Git	14.5 KB
riscv_int_controller.sv	Git	4.1 KB
riscv_L0_buffer.sv	Git	7.5 KB
riscv_load_store_unit.sv	Git	16.7 KB
riscv_mult.sv	Git	12.7 KB
riscv_pmp.sv	Git	33.3 KB
riscv_prefetch_buffer.sv	Git	12.3 KB
riscv_prefetch_L0_buffer.sv	Git	17.7 KB
riscv_register_file_latch.sv	Git	8.3 KB
riscv_register_file.sv	Git	6.1 KB
riscv_tracer.sv	Git	34.2 KB