Loading files
This file is pinned to the selected release. Download the original to open it in your design tool.
[](https://github.com/pulp-platform/common_cells/actions/workflows/ci.yml?query=branch%3Amaster)
[](CHANGELOG.md)
[](LICENSE)
# Common Cells Repository
Maintainer: Philippe Sauter <phsauter@iis.ee.ethz.ch>
This repository contains commonly used cells and headers for use in various projects.
## Cell Contents
This repository currently contains the following cells, ordered by categories.
Please note that cells with status *deprecated* are not to be used for new designs and only serve to provide compatibility with old code.
### Clocks and Resets
| Name | Description | Status | Superseded By |
|--------------------------------------------------------------------|---------------------------------------------------------------------------------------|--------------|-------------------------------------|
| [`clk_int_div`](src/clk_int_div.sv) | Arbitrary integer clock divider with config interface and 50% output clock duty cycle | active | |
| [`clk_int_div_static`](src/clk_int_div_static.sv) | A convenience wrapper around `clk_int_div` with static division factor. | active | |
| [`rstgen`](src/rstgen.sv) | Reset synchronizer | active | |
| [`rstgen_bypass`](src/rstgen_bypass.sv) | Reset synchronizer with dedicated test reset bypass | active | |
### Clock Domains and Asynchronous Crossings
| Name | Description | Status | Superseded By |
|-----------------------------------------------------------------------|-----------------------------------------------------------------------------------------------|--------------|-----------------------------------|
| [`cdc_4phase`](src/cdc_4phase.sv) | Clock domain crossing using 4-phase handshake, with ready/valid interface | active | |
| [`cdc_2phase`](src/cdc_2phase.sv) | Clock domain crossing using two-phase handshake, with ready/valid interface | active | |
| [`cdc_2phase_clearable`](src/cdc_2phase_clearable.sv) | Identical to `cdc_2phase` but supports one-sided async/sync resetting of either src or dst | active | |
| [`cdc_fifo_2phase`](src/cdc_fifo_2phase.sv) | Clock domain crossing FIFO using two-phase handshake, with ready/valid interface | active | |
| [`cdc_fifo_gray`](src/cdc_fifo_gray.sv) | Clock domain crossing FIFO using a gray-counter, with ready/valid interface | active | |
| [`cdc_fifo_gray_clearable`](src/cdc_fifo_gray_clearable.sv) | Identical to `cdc_fifo_gray` but supports one-sided async/sync resetting of either src or dst | active | |
| [`cdc_reset_ctrlr`](src/cdc_reset_ctrlr.sv) | Lock-step reset sequencer accross clock domains (internally used by clearable CDCs) | active | |
| [`clk_mux_glitch_free`](src/clk_mux_glitch_free.sv) | A glitch-free clock multiplexer with parametrizeable number of inputs. | active | |
| [`edge_detect`](src/edge_detect.sv) | Rising/falling edge detector | active | |
| [`edge_propagator`](src/edge_propagator.sv) | Propagates a single-cycle pulse across an asynchronous clock domain crossing | active | |
| [`edge_propagator_ack`](src/edge_propagator_ack.sv) | `edge_propagator` with sender-synchronous acknowledge pin (flags received pulse) | active | |
| [`edge_propagator_rx`](src/edge_propagator_rx.sv) | Receive slice of `edge_propagator`, requires only the receiver clock | active | |
| [`edge_propagator_tx`](src/edge_propagator_tx.sv) | Transmit slice of `edge_propagator`, requires only the sender clock | active | |
| [`isochronous_spill_register`](src/isochronous_spill_register.sv) | Isochronous clock domain crossing and full handshake (like `spill_register`) | active | |
| [`isochronous_4phase_handshake`](src/isochronous_4phase_handshake.sv) | Isochronous four-phase handshake. | active | |
| [`serial_deglitch`](src/serial_deglitch.sv) | Update output only after input has remained stable for a number of cycles | active | |
| [`majority_vote_filter`](src/majority_vote_filter.sv) | Smooth noisy data using a moving window threshold vote | active | |
| [`sync`](src/sync.sv) | Serial line synchronizer | active | |
| [`sync_wedge`](src/sync_wedge.sv) | Serial line synchronizer with edge detector | active | |
### Counters and Shift Registers
| Name | Description | Status | Superseded By |
| ---------------------------------------------------------- | ------------------------------------------------------------------- | ------------ | ------------------------------- |
| [`counter`](src/counter.sv) | Generic up/down counter with overflow detection | active | |
| [`credit_counter`](src/credit_counter.sv) | Up/down counter for credit | active | |
| [`delta_counter`](src/delta_counter.sv) | Up/down counter with variable delta and overflow detection | active | |
| [`lfsr_8bit`](src/lfsr_8bit.sv) | 8-bit linear feedback shift register (LFSR) | active | |
| [`lfsr_16bit`](src/lfsr_16bit.sv) | 16-bit linear feedback shift register (LFSR) | active | |
| [`lfsr`](src/lfsr.sv) | 4...64-bit parametric Galois LFSR with optional whitening feature | active | |
| [`max_counter`](src/max_counter.sv) | Up/down counter with variable delta that tracks its maximum value | active | |
| [`trip_counter`](src/trip_counter.sv) | Counter that resets automatically when it reaches a specified bound | active | |
### Data Path Elements
| Name | Description | Status | Superseded By |
|----------------------------------------------------------------|-----------------------------------------------------------------------------------------------------------|--------------|-------------------------------------|
| [`addr_decode`](src/addr_decode.sv) | Address map decoder | active | |
| [`addr_decode_dync`](src/addr_decode_dync.sv) | Address map decoder extended to support dynamic online configuration | active | |
| [`addr_decode_napot`](src/addr_decode_napot.sv) | Address map decoder using naturally-aligned power of two (NAPOT) regions | active | |
| [`multiaddr_decode`](src/multiaddr_decode.sv) | Address map decoder using NAPOT regions and allowing for multiple address inputs | active | |
| [`ecc_decode`](src/ecc_decode.sv) | SECDED Decoder (Single Error Correction, Double Error Detection) | active | |
| [`ecc_encode`](src/ecc_encode.sv) | SECDED Encoder (Single Error Correction, Double Error Detection) | active | |
| [`binary_to_gray`](src/binary_to_gray.sv) | Binary to gray code converter | active | |
| [`gray_to_binary`](src/gray_to_binary.sv) | Gray code to binary converter | active | |
| [`lzc`](src/lzc.sv) | Leading/trailing-zero counter | active | |
| [`onehot_to_bin`](src/onehot_to_bin.sv) | One-hot to binary converter | active | |
| [`shift_register`](src/shift_register.sv) | Shift register for arbitrary types | active | |
| [`shift_register_gated`](src/shift_register_gated.sv) | Shift register with ICG for arbitrary types | active | |
| [`rr_arb_tree`](src/rr_arb_tree.sv) | Round-robin arbiter for req/gnt and vld/rdy interfaces with optional priority | active | |
| [`fall_through_register`](src/fall_through_register.sv) | Fall-through register with ready/valid interface | active | |
| [`spill_register_flushable`](src/spill_register_flushable.sv) | Register with ready/valid interface to cut all combinational interface paths and additional flush signal. | active | |
| [`spill_register`](src/spill_register.sv) | Register with ready/valid interface to cut all combinational interface paths | active | |
| [`stream_arbiter`](src/stream_arbiter.sv) | Round-robin arbiter for ready/valid stream interface | active | |
| [`stream_demux`](src/stream_demux.sv) | Ready/valid interface demultiplexer | active | |
| [`lossy_valid_to_stream`](src/lossy_valid_to_stream.sv) | Convert Valid-only to ready/valid by updating in-flight transaction | active | |
| [`stream_join`](src/stream_join.sv) | Ready/valid handshake join multiple to one common | active | |
| [`stream_join_dynamic`](src/stream_join_dynamic.sv) | Ready/valid handshake join multiple to one common, dynamically configurable subset selection | active | |
| [`stream_mux`](src/stream_mux.sv) | Ready/valid interface multiplexer | active | |
| [`stream_register`](src/stream_register.sv) | Register with ready/valid interface | active | |
| [`stream_fork`](src/stream_fork.sv) | Ready/valid fork | active | |
| [`stream_fork_dynamic`](src/stream_fork_dynamic.sv) | Ready/valid fork, with selection mask for partial forking | active | |
| [`stream_filter`](src/stream_filter.sv) | Ready/valid filter | active | |
| [`stream_delay`](src/stream_delay.sv) | Randomize or delay ready/valid interface | active | |
| [`stream_to_mem`](src/stream_to_mem.sv) | Use memories without flow control for output data in streams. | active | |
| [`stream_xbar`](src/stream_xbar.sv) | Fully connected crossbar with ready/valid interface. | active | |
| [`stream_omega_net`](src/stream_omega_net.sv) | One-way stream omega-net with ready/valid interface. Isomorphic to a butterfly. | active | |
| [`stream_throttle`](src/stream_throttle.sv) | Restrict the number of outstanding transfers in a stream. | active | |
| [`sub_per_hash`](src/sub_per_hash.sv) | Substitution-permutation hash function | active | |
| [`popcount`](src/popcount.sv) | Combinatorial popcount (hamming weight) | active | |
| [`mem_to_banks_detailed`](src/mem_to_banks_detailed.sv) | Split memory access over multiple parallel banks with detailed response signals | active | |
| [`mem_to_banks`](src/mem_to_banks.sv) | Split memory access over multiple parallel banks | active | |
| [`heaviside`](src/heaviside.sv) | Generates a mask obtained by applying the Heaviside step function | active | |
| [`boxcar`](src/boxcar.sv) | Generates a mask obtained by applying a boxcar function | active | |
### Data Structures
| Name | Description | Status | Superseded By |
| ---------------------------------------------------------------- | --------------------------------------------------------------------------- | ------------ | ----------------------------------------------------------------------------------------------- |
| [`cb_filter`](src/cb_filter.sv) | Counting-Bloom-Filter with combinational lookup | active | |
| [`fifo`](src/fifo.sv) | FIFO register with generic fill counts | active | |
| [`passthrough_stream_fifo`](src/passthrough_stream_fifo.sv) | FIFO register with ready/valid interface and same-cycle push/pop when full | active | |
| [`ring_buffer`](src/ring_buffer.sv) | Ring buffer with sequential write and random-access read interfaces | active | |
| [`stream_fifo`](src/stream_fifo.sv) | FIFO register with ready/valid interface | active | |
| [`stream_fifo_optimal_wrap`](src/stream_fifo_optimal_wrap.sv) | Wrapper that optimally selects either a spill register or a FIFO | active | |
| [`plru_tree`](src/plru_tree.sv) | Pseudo least recently used tree | active | |
| [`unread`](src/unread.sv) | Empty module to sink unconnected outputs into | active | |
| [`read`](src/read.sv) | Dummy module that prevents a signal from being removed during synthesis | active | |
### Ports
Generally, modules with sequential logic receive at least the following inputs.
Intentional exceptions are clock, reset, cdc cells, and any cells that receive multiple clock inputs.
| Name | Description |
| -------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| `clk_i` | Clock driving sequential logic. |
| `rst_ni` | Asynchronous reset, active-low. Brings the module to its reset state. |
| `clr_i` | Synchronous clear, active-high. Brings the module to its reset state in the next clock cycle. Can be driven by synchronous logic or tied to `1'b0` if unused. |
### Use of Macros
Internally, the cells use macros to implement sequential logic (flip-flops) and assertions.
These macros are defined in this repo; see [RTL Register Macros](#RTL Register Macros) and [SVA Macros](#SystemVerilog Assertion Macros) below for more details.
## Header Contents
This repository currently contains the following header files.
### RTL Register Macros
The header file [`registers.svh`](include/common_cells/registers.svh) contains macros that expand to descriptions of registers.
To avoid misuse of `always_ff` blocks, only the following macros shall be used to describe sequential behavior.
The use of linter rules that flag explicit uses of `always_ff` in source code is encouraged.
| Macro | Arguments | Description |
| --------------------- | ---------------------------------------------------------------------------- | -------------------------------------------------------------------------------------------- |
| <code>`FF</code> | `q_sig`, `d_sig`, `rst_val`, (`clk_sig`, `arstn_sig`) | Flip-flop with asynchronous active-low reset |
| <code>`FFAR</code> | `q_sig`, `d_sig`, `rst_val`, (`clk_sig`, `arst_sig`) | Flip-flop with asynchronous active-high reset |
| <code>`FFARNC</code> | `q_sig`, `d_sig`, `clr_sig`, `rst_val`, (`clk_sig`, `arstn_sig`) | Flip-flop with asynchronous active-low reset and synchronous active-high clear |
| <code>`FFSR</code> | `q_sig`, `d_sig`, `rst_val`, `clk_sig`, `rst_sig` | Flip-flop with synchronous active-high reset |
| <code>`FFSRN</code> | `q_sig`, `d_sig`, `rst_val`, `clk_sig`, `rstn_sig` | Flip-flop with synchronous active-low reset |
| <code>`FFNR</code> | `q_sig`, `d_sig`, (`clk_sig`) | Flip-flop without reset |
| | | |
| <code>`FFL</code> | `q_sig`, `d_sig`, `load_ena`, `rst_val`, (`clk_sig`, `arstn_sig`) | Flip-flop with load-enable and asynchronous active-low reset |
| <code>`FFLAR</code> | `q_sig`, `d_sig`, `load_ena`, `rst_val`, (`clk_sig`, `arst_sig`) | Flip-flop with load-enable and asynchronous active-high reset |
| <code>`FFLARNC</code> | `q_sig`, `d_sig`, `load_ena`, `clr_sig`, `rst_val`, (`clk_sig`, `arstn_sig`) | Flip-flop with load-enable, asynchronous active-high reset and synchronous active-high clear |
| <code>`FFLSR</code> | `q_sig`, `d_sig`, `load_ena`, `rst_val`, `clk_sig`, `rst_sig` | Flip-flop with load-enable and synchronous active-high reset |
| <code>`FFLSRN</code> | `q_sig`, `d_sig`, `load_ena`, `rst_val`, `clk_sig`, `rstn_sig` | Flip-flop with load-enable and synchronous active-low reset |
| <code>`FFLNR</code> | `q_sig`, `d_sig`, `load_ena`, (`clk_sig`) | Flip-flop with load-enable without reset |
- *The name of the clock signal for implicit variants is `clk_i`.*
- *The name of the reset signal for implicit variants is `rst_i` or `rst_ni`, respectively for active-high and active-low variants.*
- *Argument suffix `_sig` indicates signal names for present and next state as well as clocks, resets and synchronous clear signals.*
- *Argument `rst_val` specifies the value literal to be assigned upon reset.*
- *Argument `load_ena` specifies the boolean expression that forms the load enable of the register.*
### SystemVerilog Assertion Macros
The header file [`assertions.svh`](include/common_cells/assertions.svh) contains macros that expand to assertion blocks.
These macros should recduce the effort in writing many assertions and make it
easier to use them. They are similar to but incompatible with the macros used by [lowrisc](https://github.com/lowRISC/opentitan/blob/master/hw/ip/prim/rtl/prim_assert.sv).
#### Simple Assertion and Cover Macros
| Macro | Arguments | Description |
| ------------------ | ------------------------------------------------ | -------------------------------------------------------------------------- |
| <code>`ASSERT_I</code> | `__name`, `__prop`, (`__desc`) | Immediate assertion |
| <code>`ASSERT_INIT</code> | `__name`, `__prop`, (`__desc`) | Assertion in initial block. Can be used for things like parameter checking |
| <code>`ASSERT_FINAL</code> | `__name`, `__prop`, (`__desc`) | Assertion in final block |
| <code>`ASSERT</code> | `__name`, `__prop`, (`__clk`, `__rst`, `__desc`) | Assert a concurrent property directly |
| <code>`ASSERT_NEVER</code> | `__name`, `__prop`, (`__clk`, `__rst`, `__desc`) | Assert a concurrent property NEVER happens |
| <code>`ASSERT_KNOWN</code> | `__name`, `__sig`, (`__clk`, `__rst`, `__desc`) | Concurrent clocked assertion with custom error message |
| <code>`COVER</code> | `__name`, `__prop`, (`__clk`, `__rst`) | Cover a concurrent property |
- *The name of the clock and reset signals for implicit variants is `clk_i` and `rst_ni`, respectively.*
- *`__desc` is an optional string argument describing the failure causing the assertion to be violated that is embedded into the error report and defaults to `""`.*
#### Complex Assertion Macros
| Macro | Arguments | Description |
| --------------------- | ----------------------------------------------------------------------------------- | ---------------------------------------------------------------------------------------------------------- |
| <code>`ASSERT_PULSE</code> | `__name`, `__sig`, (`__clk`, `__rst`, `__desc`) | Assert that signal is an active-high pulse with pulse length of 1 clock cycle |
| <code>`ASSERT_IF</code> | `__name`, `__prop`, `__enable`, (`__clk`, `__rst`, `__desc`) | Assert that a property is true only when an enable signal is set |
| <code>`ASSERT_KNOWN_IF</code> | `__name`, `__sig`, `__enable`, (`__clk`, `__rst`, `__desc`) | Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is set |
| <code>`ASSERT_STABLE</code> | `__name`, `__valid`, `__ready`, `__data`, `__enable`, (`__clk`, `__rst`, `__desc`) | Assert that the data on a ready-valid interface is kept stable after valid is asserted, until ready is too |
- *The name of the clock and reset signals for implicit variants is `clk_i` and `rst_ni`, respectively.*
- *`__desc` is an optional string argument describing the failure causing the assertion to be violated that is embedded into the error report and defaults to `""`.*
#### Assumption Macros
| Macro | Arguments | Description |
| -------------- | ------------------------------------------------ | ---------------------------- |
| <code>`ASSUME</code> | `__name`, `__prop`, (`__clk`, `__rst`, `__desc`) | Assume a concurrent property |
| <code>`ASSUME_I</code> | `__name`, `__prop`, (`__desc`) | Assume an immediate property |
- *The name of the clock and reset signals for implicit variants is `clk_i` and `rst_ni`, respectively.*
- *`__desc` is an optional string argument describing the failure causing the assertion to be violated that is embedded into the error report and defaults to `""`.*
#### Formal Verification Macros
| Macro | Arguments | Description |
| ------------------ | ------------------------------------------------ | ------------------------------------------------------------ |
| <code>`ASSUME_FPV</code> | `__name`, `__prop`, (`__clk`, `__rst`, `__desc`) | Assume a concurrent property during formal verification only |
| <code>`ASSUME_I_FPV</code> | `__name`, `__prop`, (`__desc`) | Assume a concurrent property during formal verification only |
| <code>`COVER_FPV</code> | `__name`, `__prop`, (`__clk`, `__rst`) | Cover a concurrent property during formal verification |
- *The name of the clock and reset signals for implicit variants is `clk_i` and `rst_ni`, respectively.*
- *`__desc` is an optional string argument describing the failure causing the assertion to be violated that is embedded into the error report and defaults to `""`.*
4f62c83c0This file is pinned to the selected release. Download the original to open it in your design tool.