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v 20130925 2
C 40000 40000 0 0 0 title-B.sym
N 45400 41800 45400 41500 4
N 45400 41500 46900 41500 4
N 45700 41800 45700 41500 4
N 46000 41800 46000 41500 4
N 46900 41800 46900 41500 4
N 46600 41800 46600 41500 4
N 46300 41800 46300 41500 4
N 45500 50200 45500 50400 4
N 41800 50400 46700 50400 4
N 46700 50200 46700 50400 4
N 46400 50200 46400 50400 4
N 46100 50200 46100 50400 4
N 45800 50200 45800 50400 4
C 47450 41100 1 0 0 crystal.sym
{
T 47650 41600 5 10 0 0 0 0 1
device=CRYSTAL ABLS-16.000MHZ-B4-T
T 47500 41350 5 10 1 1 0 0 1
refdes=X1
T 47350 40950 5 10 1 1 0 0 1
value=16MHz
T 47450 41100 5 10 0 0 0 0 1
model=ABLS-16.000MHZ-B4-T
T 47450 41100 5 10 0 0 0 0 1
description=Crystal 16.0000MHz 30ppm 18pF 40 Ohm -20°C - 70°C Surface Mount HC49/US
T 47450 41100 5 10 0 0 0 0 1
footprint=Crystal_HC49
}
C 47400 40500 1 90 0 cap.sym
{
T 46700 40700 5 10 0 0 90 0 1
device=CAPACITOR
T 46900 40900 5 10 1 1 0 0 1
refdes=C33
T 47250 40700 5 10 1 1 180 0 1
value=10pF
T 47400 40500 5 10 0 0 90 0 1
footprint=0805_ext
T 47400 40500 5 10 0 0 0 0 1
model=C0805C100J5GACTU
}
C 48100 40500 1 90 0 cap.sym
{
T 47400 40700 5 10 0 0 90 0 1
device=CAPACITOR
T 48150 40800 5 10 1 1 0 0 1
refdes=C34
T 48600 40700 5 10 1 1 180 0 1
value=10pF
T 48100 40500 5 10 0 0 270 0 1
footprint=0805_ext
T 48100 40500 5 10 0 0 0 0 1
model=C0805C100J5GACTU
}
N 48000 41000 48000 41800 4
N 48000 41800 47800 41800 4
N 47300 41000 47300 41800 4
N 47300 41800 47500 41800 4
C 41000 40400 1 0 0 pdi.sym
{
T 41300 42300 5 10 1 1 0 0 1
refdes=ISP
T 41000 40400 5 10 0 0 0 0 1
footprint=ISP
T 41000 40400 5 10 0 0 0 0 1
description=Harwin M20-9950345, DIL VERTICAL PC TAIL PIN HEADER , .1" pitch, male connector
T 41000 40400 5 10 0 1 0 0 1
device=HEADER_6 M20-9980346
T 41000 40400 5 10 0 0 0 0 1
model=M20-9980346
T 41000 40400 5 10 0 0 0 0 1
value=6-Pin Header
}
N 44600 41500 44600 41800 4
N 44600 41500 43900 41500 4
N 43900 41500 43900 42000 4
N 43900 42000 42200 42000 4
N 42200 40800 44900 40800 4
N 44900 40800 44900 41800 4
C 42500 41500 1 180 0 nc.sym
{
T 42400 41000 5 10 0 0 180 0 1
value=NoConnection
T 42400 40800 5 10 0 0 180 0 1
device=DRC_Directive
}
C 42500 41200 1 180 0 nc.sym
{
T 42400 40700 5 10 0 0 180 0 1
value=NoConnection
T 42400 40500 5 10 0 0 180 0 1
device=DRC_Directive
}
T 50000 40700 9 10 1 0 0 0 2
Microprocessor
Copyright (c) 2016-2019, Buildbotics LLC
T 53900 40100 9 10 1 0 0 0 1
Doug & Joe Coffland
T 53800 40400 9 10 1 0 0 0 1
Micro rev 1.0
C 43800 41700 1 0 0 ATXmegaA3.sym
{
T 47200 50200 5 8 0 0 0 0 1
footprint=TQFP64_14_ATXMEGA
T 47800 50200 5 10 1 1 0 0 1
refdes=U5
T 45200 49100 5 10 1 1 0 0 1
device=ATXMEGA192A3U-AUR
T 43800 41700 5 10 0 1 0 0 1
model=ATXMEGA192A3U-AU
T 43800 41700 5 10 0 0 0 0 1
value=ATXMEGA192A3U-AUR
}
C 41300 50300 1 0 0 cap.sym
{
T 41500 51000 5 10 0 0 0 0 1
device=CAPACITOR C0805C104M5RACTU
T 41700 50650 5 10 1 1 180 0 1
refdes=C27
T 41500 51200 5 10 0 0 0 0 1
symversion=0.1
T 41300 50150 5 10 1 1 0 0 1
value=0.1uF
T 41300 50300 5 10 0 0 0 0 1
footprint=0805_ext
T 41300 50300 5 10 0 0 0 0 1
model=C0805C104M5RACTU
T 41300 50300 5 10 0 0 0 0 1
description=Kemet ceramic 50 volt cap
}
N 48000 41200 47850 41200 4
N 47300 41200 47450 41200 4
N 48000 40500 47300 40500 4
N 47300 40500 47300 40600 4
N 48000 40500 48000 40600 4
N 40800 50400 41400 50400 4
N 45000 50200 45000 50400 4
C 41300 49700 1 0 0 cap.sym
{
T 41500 50400 5 10 0 0 0 0 1
device=CAPACITOR C0805C104M5RACTU
T 41700 50050 5 10 1 1 180 0 1
refdes=C28
T 41500 50600 5 10 0 0 0 0 1
symversion=0.1
T 41300 49550 5 10 1 1 0 0 1
value=0.1uF
T 41300 49700 5 10 0 0 0 0 1
footprint=0805_ext
T 41300 49700 5 10 0 0 0 0 1
model=C0805C104M5RACTU
T 41300 49700 5 10 0 0 0 0 1
description=Kemet ceramic 50 volt cap
}
C 41300 49100 1 0 0 cap.sym
{
T 41500 49800 5 10 0 0 0 0 1
device=CAPACITOR C0805C104M5RACTU
T 41700 49450 5 10 1 1 180 0 1
refdes=C29
T 41500 50000 5 10 0 0 0 0 1
symversion=0.1
T 41300 48950 5 10 1 1 0 0 1
value=0.1uF
T 41300 49100 5 10 0 0 0 0 1
footprint=0805_ext
T 41300 49100 5 10 0 0 0 0 1
model=C0805C104M5RACTU
T 41300 49100 5 10 0 0 0 0 1
description=Kemet ceramic 50 volt cap
}
C 41300 48400 1 0 0 cap.sym
{
T 41500 49100 5 10 0 0 0 0 1
device=CAPACITOR C0805C104M5RACTU
T 41700 48750 5 10 1 1 180 0 1
refdes=C30
T 41500 49300 5 10 0 0 0 0 1
symversion=0.1
T 41300 48250 5 10 1 1 0 0 1
value=0.1uF
T 41300 48400 5 10 0 0 0 0 1
footprint=0805_ext
T 41300 48400 5 10 0 0 0 0 1
model=C0805C104M5RACTU
T 41300 48400 5 10 0 0 0 0 1
description=Kemet ceramic 50 volt cap
}
C 41300 47700 1 0 0 cap.sym
{
T 41500 48400 5 10 0 0 0 0 1
device=CAPACITOR C0805C104M5RACTU
T 41700 48050 5 10 1 1 180 0 1
refdes=C31
T 41500 48600 5 10 0 0 0 0 1
symversion=0.1
T 41300 47550 5 10 1 1 0 0 1
value=0.1uF
T 41300 47700 5 10 0 0 0 0 1
footprint=0805_ext
T 41300 47700 5 10 0 0 0 0 1
model=C0805C104M5RACTU
T 41300 47700 5 10 0 0 0 0 1
description=Kemet ceramic 50 volt cap
}
N 41800 47200 41800 50400 4
N 41400 47200 41400 50400 4
C 41300 47100 1 0 0 cap.sym
{
T 41500 47800 5 10 0 0 0 0 1
device=CAPACITOR C0805C104M5RACTU
T 41700 47450 5 10 1 1 180 0 1
refdes=C32
T 41500 48000 5 10 0 0 0 0 1
symversion=0.1
T 41300 46950 5 10 1 1 0 0 1
value=0.1uF
T 41300 47100 5 10 0 0 0 0 1
footprint=0805_ext
T 41300 47100 5 10 0 0 0 0 1
model=C0805C104M5RACTU
T 41300 47100 5 10 0 0 0 0 1
description=Kemet ceramic 50 volt cap
}
C 43200 46400 1 180 1 input.sym
{
T 43200 46100 5 10 0 0 180 6 1
device=INPUT
T 43450 46250 5 10 1 1 0 6 1
net=max_a:1
}
C 43200 46700 1 180 1 input.sym
{
T 43200 46400 5 10 0 0 180 6 1
device=INPUT
T 43450 46550 5 10 1 1 0 6 1
net=min_a:1
}
C 43200 45200 1 180 1 input.sym
{
T 43200 44900 5 10 0 0 180 6 1
device=INPUT
T 43450 45050 5 10 1 1 0 6 1
net=max_z:1
}
C 43200 45500 1 180 1 input.sym
{
T 43200 45200 5 10 0 0 180 6 1
device=INPUT
T 43450 45350 5 10 1 1 0 6 1
net=min_z:1
}
C 43200 45800 1 180 1 input.sym
{
T 43200 45500 5 10 0 0 180 6 1
device=INPUT
T 43450 45650 5 10 1 1 0 6 1
net=max_y:1
}
C 43200 46100 1 180 1 input.sym
{
T 43200 45800 5 10 0 0 180 6 1
device=INPUT
T 43450 45950 5 10 1 1 0 6 1
net=min_y:1
}
C 48300 47300 1 180 1 output.sym
{
T 48400 47000 5 10 0 0 180 6 1
device=OUTPUT
T 48850 47150 5 10 1 1 0 0 1
net=step_y:1
}
C 48300 46400 1 180 1 output.sym
{
T 48400 46100 5 10 0 0 180 6 1
device=OUTPUT
T 48850 46250 5 10 1 1 0 0 1
net=dir_y:1
}
C 48300 44700 1 180 1 output.sym
{
T 48400 44400 5 10 0 0 180 6 1
device=OUTPUT
T 48850 44550 5 10 1 1 0 0 1
net=step_z:1
}
C 48300 45500 1 180 1 output.sym
{
T 48400 45200 5 10 0 0 180 6 1
device=OUTPUT
T 48850 45350 5 10 1 1 0 0 1
net=dir_z:1
}
C 48300 46100 1 180 1 output.sym
{
T 48400 45800 5 10 0 0 180 6 1
device=OUTPUT
T 48850 45950 5 10 1 1 0 0 1
net=step_a:1
}
C 48300 45200 1 180 1 output.sym
{
T 48400 44900 5 10 0 0 180 6 1
device=OUTPUT
T 48850 45050 5 10 1 1 0 0 1
net=dir_a:1
}
C 44000 44100 1 180 0 output.sym
{
T 43900 43800 5 10 0 0 180 0 1
device=INPUT
T 42600 43950 5 10 1 1 0 0 1
net=serial_tx:1
}
C 43200 43600 1 0 0 input.sym
{
T 43200 43900 5 10 0 0 0 0 1
device=OUTPUT
T 42600 43650 5 10 1 1 0 0 1
net=serial_rx:1
}
C 43200 47100 1 0 0 input.sym
{
T 43200 47400 5 10 0 0 0 0 1
device=INPUT
T 42800 47150 5 10 1 1 0 0 1
net=min_x:1
}
C 43200 46800 1 0 0 input.sym
{
T 43200 47100 5 10 0 0 0 0 1
device=INPUT
T 42750 46850 5 10 1 1 0 0 1
net=max_x:1
}
C 48300 46700 1 180 1 output.sym
{
T 48400 46400 5 10 0 0 180 6 1
device=OUTPUT
T 49400 46550 5 10 1 1 0 6 1
net=dir_x:1
}
C 45700 40900 1 180 0 input.sym
{
T 45700 40600 5 10 0 0 180 0 1
device=OUTPUT
T 46000 40900 5 10 1 1 180 0 1
net=reset:1
}
C 44000 43500 1 180 0 output.sym
{
T 43900 43200 5 10 0 0 180 0 1
device=OUTPUT
T 42500 43350 5 10 1 1 0 0 1
net=serial_cts:1
}
C 48300 45600 1 0 0 output.sym
{
T 48400 45900 5 10 0 0 0 0 1
device=OUTPUT
T 49550 45800 5 10 1 1 180 0 1
net=load_1:1
}
C 49100 47900 1 0 1 input.sym
{
T 49100 48200 5 10 0 0 0 6 1
device=OUTPUT
T 49750 47950 5 10 1 1 0 6 1
net=rs485_ro:1
}
C 48300 48200 1 0 0 output.sym
{
T 48400 48500 5 10 0 0 0 0 1
device=OUTPUT
T 49575 48400 5 10 1 1 180 0 1
net=load_2:1
}
C 46400 50400 1 0 0 3.3V_motor.sym
{
T 46500 51100 5 10 0 0 0 0 1
device=none
}
C 42200 42000 1 270 0 3.3V_motor.sym
{
T 42900 41900 5 10 0 0 270 0 1
device=none
}
C 48300 43900 1 0 0 output.sym
{
T 48400 44200 5 10 0 0 0 0 1
device=INPUT
T 49350 44075 5 10 1 1 180 0 1
net=fault:1
}
C 47600 40200 1 0 0 gnd.sym
C 46000 41200 1 0 0 gnd.sym
C 42500 40400 1 90 0 gnd.sym
C 40700 50100 1 0 0 gnd.sym
C 48300 47800 1 180 1 output.sym
{
T 48400 47500 5 10 0 0 180 6 1
device=INPUT
T 49725 47650 5 10 1 1 0 6 1
net=rs485_di:1
}
C 44000 48400 1 180 0 output.sym
{
T 43900 48100 5 10 0 0 180 0 1
device=INPUT
T 42300 48250 5 10 1 1 0 0 1
net=spin_enable:1
}
C 49100 43800 1 180 0 input.sym
{
T 49100 43500 5 10 0 0 180 0 1
device=OUTPUT
T 48850 43650 5 10 1 1 0 0 1
net=estop:1
}
C 48300 49900 1 180 1 output.sym
{
T 48400 49600 5 10 0 0 180 6 1
device=OUTPUT
T 49550 49750 5 10 1 1 0 6 1
net=step_x:1
}
C 48300 48700 1 180 1 output.sym
{
T 48400 48400 5 10 0 0 180 6 1
device=INPUT
T 49825 48550 5 10 1 1 0 6 1
net=spin_pwm:1
}
C 44000 48700 1 180 0 output.sym
{
T 43900 48400 5 10 0 0 180 0 1
device=INPUT
T 42650 48550 5 10 1 1 0 0 1
net=spin_dir:1
}
C 48300 44400 1 180 1 output.sym
{
T 48400 44100 5 10 0 0 180 6 1
device=INPUT
T 49725 44250 5 10 1 1 0 6 1
net=rs485_rw:1
}
C 43200 47900 1 0 0 input.sym
{
T 43200 48200 5 10 0 0 0 0 1
device=INPUT
T 42525 47950 5 10 1 1 0 0 1
net=analog_1:1
}
C 43200 44200 1 0 0 input.sym
{
T 43200 44500 5 10 0 0 0 0 1
device=OUTPUT
T 43050 44250 5 10 1 1 0 0 1
net=scl:1
}
C 44000 44700 1 180 0 io.sym
{
T 44000 44100 5 10 0 0 180 0 1
device=IO
T 43000 44525 5 10 1 1 0 0 1
net=sda:1
}
C 49100 42600 1 180 0 input.sym
{
T 49100 42300 5 10 0 0 180 0 1
device=INPUT
T 49500 42550 5 10 1 1 180 0 1
net=probe:1
}
C 43200 47600 1 0 0 input.sym
{
T 43200 47900 5 10 0 0 0 0 1
device=INPUT
T 42525 47650 5 10 1 1 0 0 1
net=analog_2:1
}
C 44000 49900 1 180 0 output.sym
{
T 43900 49600 5 10 0 0 180 0 1
device=INPUT
T 42550 49750 5 10 1 1 0 0 1
net=enable_x:1
}
C 44000 49600 1 180 0 output.sym
{
T 43900 49300 5 10 0 0 180 0 1
device=INPUT
T 42550 49450 5 10 1 1 0 0 1
net=enable_y:1
}
C 44000 49300 1 180 0 output.sym
{
T 43900 49000 5 10 0 0 180 0 1
device=INPUT
T 42550 49150 5 10 1 1 0 0 1
net=enable_z:1
}
C 44000 49000 1 180 0 output.sym
{
T 43900 48700 5 10 0 0 180 0 1
device=INPUT
T 42550 48850 5 10 1 1 0 0 1
net=enable_a:1
}
C 52500 44700 1 0 0 header12-2.sym
{
T 52500 46400 5 10 0 1 0 0 1
device=HEADER12
T 53100 47200 5 10 1 1 0 0 1
refdes=IO
T 52500 44700 5 10 0 0 0 0 1
footprint=HEADER12_2
}
C 52200 47000 1 270 0 gnd.sym
C 53900 47200 1 270 0 3.3V_motor.sym
{
T 54600 47100 5 10 0 0 270 0 1
device=none
}
C 48300 43300 1 0 0 io.sym
{
T 48300 43900 5 10 0 0 0 0 1
device=IO
T 48850 43375 5 10 1 1 0 0 1
net=pf4:1
}
C 48300 43000 1 0 0 io.sym
{
T 48300 43600 5 10 0 0 0 0 1
device=IO
T 48850 43050 5 10 1 1 0 0 1
net=pf5:1
}
C 48300 46800 1 0 0 io.sym
{
T 48300 47400 5 10 0 0 0 0 1
device=IO
T 48850 46875 5 10 1 1 0 0 1
net=pe1:1
}
C 48300 48800 1 0 0 io.sym
{
T 48300 49400 5 10 0 0 0 0 1
device=IO
T 48850 48875 5 10 1 1 0 0 1
net=pd3:1
}
C 48300 49100 1 0 0 io.sym
{
T 48300 49700 5 10 0 0 0 0 1
device=IO
T 48850 49175 5 10 1 1 0 0 1
net=pd2:1
}
C 48300 49400 1 0 0 io.sym
{
T 48300 50000 5 10 0 0 0 0 1
device=IO
T 48850 49475 5 10 1 1 0 0 1
net=pd1:1
}
C 44000 43200 1 180 0 io.sym
{
T 44000 42600 5 10 0 0 180 0 1
device=IO
T 43450 43175 5 10 1 1 180 0 1
net=mosi:1
}
C 44000 42900 1 180 0 io.sym
{
T 44000 42300 5 10 0 0 180 0 1
device=IO
T 43450 42875 5 10 1 1 180 0 1
net=miso:1
}
C 44000 42600 1 180 0 io.sym
{
T 44000 42000 5 10 0 0 180 0 1
device=IO
T 43450 42575 5 10 1 1 180 0 1
net=sck:1
}
C 53900 44800 1 0 0 io.sym
{
T 53900 45400 5 10 0 0 0 0 1
device=IO
T 54450 44825 5 10 1 1 0 0 1
net=sck:1
}
C 52500 46600 1 180 0 io.sym
{
T 52500 46000 5 10 0 0 180 0 1
device=IO
T 51950 46550 5 10 1 1 180 0 1
net=pf5:1
}
C 52500 46200 1 180 0 io.sym
{
T 52500 45600 5 10 0 0 180 0 1
device=IO
T 51950 46125 5 10 1 1 180 0 1
net=pf4:1
}
C 53900 46000 1 0 0 io.sym
{
T 53900 46600 5 10 0 0 0 0 1
device=IO
T 54450 46075 5 10 1 1 0 0 1
net=pe1:1
}
C 52500 45800 1 180 0 io.sym
{
T 52500 45200 5 10 0 0 180 0 1
device=IO
T 51950 45725 5 10 1 1 180 0 1
net=pd3:1
}
C 52500 45400 1 180 0 io.sym
{
T 52500 44800 5 10 0 0 180 0 1
device=IO
T 51950 45325 5 10 1 1 180 0 1
net=pd2:1
}
C 52500 45000 1 180 0 io.sym
{
T 52500 44400 5 10 0 0 180 0 1
device=IO
T 51950 44925 5 10 1 1 180 0 1
net=pd1:1
}
C 53900 45600 1 0 0 io.sym
{
T 53900 46200 5 10 0 0 0 0 1
device=IO
T 54450 45625 5 10 1 1 0 0 1
net=mosi:1
}
C 53900 45200 1 0 0 io.sym
{
T 53900 45800 5 10 0 0 0 0 1
device=IO
T 54450 45225 5 10 1 1 0 0 1
net=miso:1
}
C 48300 42700 1 0 0 io.sym
{
T 48300 43300 5 10 0 0 0 0 1
device=IO
T 48850 42750 5 10 1 1 0 0 1
net=pf6:1
}
C 53900 46400 1 0 0 io.sym
{
T 53900 47000 5 10 0 0 0 0 1
device=IO
T 54450 46450 5 10 1 1 0 0 1
net=pf6:1
}