Amigo 1000 - Conversion of the Amiga 1000 schematic into Verilog 2001 RTL
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Amigo - Amiga 1000, in Verilog 2001, from schematic
Copyright 2010, Jason S. McMullan
The aim of the Amigo is to create a schematic-level capture of the digital components of the Commodore Amiga 1000.
My personal reason for this project is to have a functional Verilog simulation that can be used to:
The last point seems to be the most important for me. All of the Amiga 1000 schematics I have been able to obtain online are very blurry, almost to the point of unreadability.
My hope is that the 'Amigo' will be able to be used to generate a faithful and readable schematic one day.
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Progress so far:
Selectable Wishbone cores for emulating the Motorola 68000
ao68000 (from OpenCores)
ucore (from OpenCores)
Any other Wishbone complaint 32-bit CPU core should be pluggable, via the 'Motorola_16_to_w32.v' module and a small amount of glue logic for interrupts.
Amiga 1000 Daughterboard logic appears to be complete
Things to do:
Create wrappers for Minimig's OCS cores (Paula, Agnus, Denise), to leverage the Minimig work for Amigo.
Decide upon (for REAL!) whether to make the first pass of the Amigo 1000 a Rev A or a Rev C machine.
Finish out the Amigo capture, including pullup resistors, ferrite beads, etc.
Decide what to do about the analog components (ie RGB to NTSC conversion circuity). Icarus Verlog doesn't (as of 0.9.x) support Verilog-AMS, so I may have to put that off.