ahb-tl-bridge

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README.mdView source

Introduction

This project contains SystemVerilog code for the AHB to TileLink UL (Uncached Lightweight) bridge.

Features

Implemented features:

Write strobe
Dynamic size
Only implemented bridge so far is for matching data widths

Testing

The bridge is tested using the cocotb co-simulation framework. Transactions were tests with the use of the AHB and TL BFMs (Bus functional models) implemented in cocotb-TileLink and cocotb-AHB respectively.

To run the tests run make. By default Verilator will be used for simulation, but can be overriden with the SIM flag, e.g. make SIM=SimOfYourChoice.

SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge

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