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aes

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Removed unneeded addresses.

Joachim Strömbergson · Jan 26, 2018, 3:08 PM UTC

58892345c828

Fixed one bit value declaration to silence parser warnings about truncated values in some parsers.

Joachim Strömbergson · Apr 12, 2017, 1:24 PM UTC

c3e52b5d6e6b

Changed API logic for result reg to use Verilog bit slicing. Removed readout of key and block.

Joachim Strömbergson · Jan 18, 2017, 7:13 AM UTC

81d6e2d26fff

Changed block regs into array and simplified RTL for API.

Joachim Strömbergson · Jan 17, 2017, 7:12 AM UTC

d947832ca8b2

HEADSUP: This commit changes order of API config and status address to match what is used in other cores. VERSION updated to reflect API change. NAME change to remove incorrect notion that the core only is 128 bit capable.

Joachim Strömbergson · Nov 20, 2016, 7:48 AM UTC

c5135c56e66e

Removed the error port.

Joachim Strömbergson · Nov 19, 2016, 8:20 AM UTC

f4468c1b8451

First stage cleanup: Changed key registers into array.

Joachim Strömbergson · Nov 17, 2016, 7:32 AM UTC

8e859ee8e99f

Fixed long constant declarations handled by Verilog extend rules.

Joachim Strömbergson · May 21, 2016, 6:58 AM UTC

9cc308eb6c6c

Simplified the logic for handling control bits that are automatically cleared.

Joachim Strömbergson · May 11, 2016, 6:20 AM UTC

ee55bc7380b0

Removed redundant Verilog block statements and compacted the code.

Joachim Strömbergson · Mar 10, 2016, 7:28 AM UTC

ee76519e28da

Changed to localparam.

Joachim Strömbergson · Apr 17, 2015, 11:29 AM UTC

b7d54bc7667b

Corrected where the bits for encdec and key length are located.

Joachim Strömbergson · Nov 27, 2014, 1:49 PM UTC

b087f3eb5867